diff options
| author | Samsp_Liu <Samsp_Liu@compal.corp-partner.google.com> | 2020-07-22 16:21:20 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-09-02 04:19:10 +0000 |
| commit | 074b0e363491af9c82c9d54fa0c84b8df9ec2e1e (patch) | |
| tree | 4bcd68b1f6a54959332fdd442bfc52780f7ef616 /board/halvor/board.h | |
| parent | cd17b934942a3ca602d6eadf38ed3ed95b55ef4c (diff) | |
| download | chrome-ec-074b0e363491af9c82c9d54fa0c84b8df9ec2e1e.tar.gz | |
Halvor: Need to Implement three USB-C function
The PD function can be enabled.
BUG=b:153705222
BRANCH=none
TEST=Enable Halvor PD Port 0,Port 1 and Port 2
Change-Id: Id171e7c9f900098b2b727e4f69479ee49ea995b3
Signed-off-by: Samsp_Liu <Samsp_Liu@compal.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2311998
Tested-by: SamSP Liu <samsp_liu@compal.corp-partner.google.com>
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
Commit-Queue: SamSP Liu <samsp_liu@compal.corp-partner.google.com>
Diffstat (limited to 'board/halvor/board.h')
| -rw-r--r-- | board/halvor/board.h | 17 |
1 files changed, 12 insertions, 5 deletions
diff --git a/board/halvor/board.h b/board/halvor/board.h index d684bd1b5f..367668fbcd 100644 --- a/board/halvor/board.h +++ b/board/halvor/board.h @@ -42,7 +42,7 @@ (BIT(LID_ACCEL) | BIT(CLEAR_ALS)) /* USB Type C and USB PD defines */ -#define CONFIG_USB_PD_PORT_MAX_COUNT 2 +#define CONFIG_USB_PD_PORT_MAX_COUNT 3 /* * USB-C port's USB2 & USB3 mapping from schematics @@ -50,10 +50,12 @@ * USB3 numbering on AP - 0 to n (PMC's USB3 numbering for MUX * configuration is - 1 to n hence add +1) */ -#define USBC_PORT_0_USB2_NUM 9 +#define USBC_PORT_0_USB2_NUM 2 #define USBC_PORT_0_USB3_NUM 1 #define USBC_PORT_1_USB2_NUM 4 #define USBC_PORT_1_USB3_NUM 2 +#define USBC_PORT_2_USB2_NUM 6 +#define USBC_PORT_2_USB3_NUM 3 #define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ @@ -73,13 +75,14 @@ /* Enabling USB4 mode */ #define CONFIG_USB_PD_USB4 -#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x40 +#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x40 +#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x41 +#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR 0x42 /* USB Type A Features */ /* USBC PPC*/ -#define CONFIG_USBC_PPC_SN5S330 /* USBC port C0 */ -#define CONFIG_USBC_PPC_SYV682X /* USBC port C1 */ +#define CONFIG_USBC_PPC_SYV682X /* USBC port C0 C1 C2 */ /* BC 1.2 */ @@ -115,6 +118,9 @@ #define GPIO_RSMRST_L_PGOOD GPIO_PG_EC_RSMRST_ODL #define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL #define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_USB_C0_BC12_INT_ODL GPIO_USB_C0_MIX_INT_ODL +#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL +#define GPIO_USB_C2_BC12_INT_ODL GPIO_USB_C2_MIX_INT_ODL #define GPIO_WP_L GPIO_EC_WP_L #define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L @@ -169,6 +175,7 @@ enum sensor_id { enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, + USBC_PORT_C2, USBC_PORT_COUNT }; |