diff options
| author | Keith Short <keithshort@chromium.org> | 2020-04-06 17:27:06 -0600 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-04-08 01:34:59 +0000 |
| commit | b3c3f6a8f4b8f0bfebb5a0c3c1ea9468bf4d29dd (patch) | |
| tree | 2c8b62e600a4b5e64bf4a3cdc91342ae72edbd16 /board/halvor | |
| parent | 0917820678ee1f66a71d88e15e1f8f96e3c72000 (diff) | |
| download | chrome-ec-b3c3f6a8f4b8f0bfebb5a0c3c1ea9468bf4d29dd.tar.gz | |
halvor: Remove GPIOs only used by Volteer board version 0
Remove obsolete configuration of pins GPIO75 and GPO32.
BUG=b:149858568
BRANCH=none
TEST=make buildall
Change-Id: I7be28a7b8cd441f346dd357bb99bd15086ce677b
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2138148
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
Diffstat (limited to 'board/halvor')
| -rw-r--r-- | board/halvor/gpio.inc | 15 |
1 files changed, 0 insertions, 15 deletions
diff --git a/board/halvor/gpio.inc b/board/halvor/gpio.inc index 454b4f1bcd..19da03aa61 100644 --- a/board/halvor/gpio.inc +++ b/board/halvor/gpio.inc @@ -48,13 +48,6 @@ GPIO_INT(USB_C1_MIX_INT_ODL, PIN(0, 3), GPIO_INT_BOTH, bc12_interrupt) /* Volume button interrupts */ GPIO_INT(EC_VOLDN_BTN_ODL, PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) -/* - * EC_VOLUP_BTN_ODL moved from GPIO75 to GPIO97 on boards with board ID >=1. - * GPIO97/EN_PP1050_BYPASS is DNS on board ID 0, and GPIO75 will be used once - * EFS support is added. - * TODO (b/149858568): remove board ID=0 support. - */ -GPIO_INT(EC_VOLUP_BTN_ODL_BOARDID_0, PIN(7, 5), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) GPIO_INT(EC_VOLUP_BTN_ODL, PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) /* Power Sequencing Signals */ @@ -100,14 +93,6 @@ GPIO(SYS_RST_ODL, PIN(C, 5), GPIO_ODR_HIGH) GPIO(EC_PCH_INT_ODL, PIN(B, 0), GPIO_ODR_HIGH) /* USB and USBC Signals */ - -/* - * USB_C1 moved from GPIO32 to GPIO83 on boards with board ID >=1. - * GPIO83/EN_PP1800_A is DNS on board ID 0 and GPIO32 is N/C on board ID >=1 - * so it's safe to define GPIOs compatible with both designs. - * TODO (b/149858568): remove board ID=0 support. - */ -GPIO(USB_C1_RT_RST_ODL_BOARDID_0, PIN(3, 2), GPIO_ODR_LOW) /* USB_C1 Reset on boards without board ID */ GPIO(USB_C1_RT_RST_ODL, PIN(8, 3), GPIO_ODR_LOW) /* USB_C1 Reset on boards board ID >=1 */ /* Don't have a load switch for retimer */ |