diff options
| author | Furquan Shaikh <furquan@google.com> | 2019-04-04 11:10:39 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2019-04-09 06:20:01 -0700 |
| commit | 4c60f22507aebfe25c92848cd51fe5b20d479a4c (patch) | |
| tree | 1df6984a1b87d339e5fd18227bd75b3a6d56295b /board/hatch | |
| parent | 8530e53965b9eb8cc18d9fd9fdae2cadb6dcc8c3 (diff) | |
| download | chrome-ec-4c60f22507aebfe25c92848cd51fe5b20d479a4c.tar.gz | |
hatch: Configure EC_INT_L as low before entering S5/G3
EC_INT_L on hatch is a push-pull line driven by EC and going to SoC
GPIO. Having this driven high in G3 results in leakage on PP3300_A_SOC
rail. This change configures EC_INT_L to drive it low on entering S5
and re-configures it to drive high on exiting S5.
BUG=b:129306003
BRANCH=None
TEST=Verified that SLP_S0_L, EC_INT_L and SYS_RESET_L are pulled low
in G3.
Change-Id: I9b00eef72762b9d16afc42723e8985d752f83c55
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1553562
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Rachel Nancollas <rachelsn@google.com>
Reviewed-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Diffstat (limited to 'board/hatch')
| -rw-r--r-- | board/hatch/board.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/board/hatch/board.c b/board/hatch/board.c index 29867bcfa8..ae4a26aad4 100644 --- a/board/hatch/board.c +++ b/board/hatch/board.c @@ -386,3 +386,25 @@ void board_overcurrent_event(int port, int is_overcurrented) /* Note that the level is inverted because the pin is active low. */ gpio_set_level(GPIO_USB_C_OC_ODL, !is_overcurrented); } + +/* Called on AP S5 -> S3 transition */ +static void board_chipset_startup(void) +{ + gpio_set_level(GPIO_EC_INT_L, 1); +} +DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, + HOOK_PRIO_DEFAULT); + +/* Called on AP S3 -> S5 transition */ +static void board_chipset_shutdown(void) +{ + /* + * EC_INT_L is currently a push-pull pin and this causes leakage in G3 + * onto the PP3300_A_SOC rail. Pull this pin low when host enters S5 to + * avoid the leakage. It will be pulled back high when host transitions + * out of S5. + */ + gpio_set_level(GPIO_EC_INT_L, 0); +} +DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, + HOOK_PRIO_DEFAULT); |