bloonchipper: Refactor GPIOs to keep RO minimal

We want the amount of code and number of things defined in RO to be as
minimal as possible since RO is frozen forever. By keeping RO minimal,
we can reduce surface area for attacks and also confusion when GPIOs are
removed or renamed.

The fingerprint-related code only runs in RW, so move all
fingerprint-related GPIOs and associated code into separate files that
are only included in RW.

BRANCH=none
BUG=b:178746753
TEST=On dragonclaw v0.2 with servo micro and jtrace, verify sensor ID
     shows on console
TEST=On dragonair, test fingerprint enroll and unlock
TEST=On morphius, test fingerprint enroll and unlock

Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: Ia6791666b57ed9be81230d8a5f77d874f56da5a4
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2673909
Reviewed-by: Craig Hesling <hesling@chromium.org>

9 files changed, 200 insertions, 130 deletions

diff --git a/board/hatch_fp/board.c b/board/hatch_fp/board.c
index 8bdc4cf190..c2a2e32107 100644
--- a/board/hatch_fp/board.c
+++ b/board/hatch_fp/board.c
@@ -13,13 +13,6 @@
 #include "system.h"
 #include "task.h"
 #include "usart_host_command.h"
-#include "util.h"
-
-/*
- * Some platforms have a broken SLP_S0_L signal (stuck to 0 in S0)
- * if set, ignore it and only uses SLP_S3_L for the AP state.
- */
-static bool broken_slp_s0;
 
 /**
  * Disable restricted commands when the system is locked.
@@ -31,79 +24,16 @@ int console_is_restricted(void)
 	return system_is_locked();
 }
 
-#ifndef HAS_TASK_FPSENSOR
-void fps_event(enum gpio_signal signal)
-{
-}
-#endif
-
-static void ap_deferred(void)
-{
-	/*
-	 * in S3:   SLP_S3_L is 0 and SLP_S0_L is X.
-	 * in S0ix: SLP_S3_L is 1 and SLP_S0_L is 0.
-	 * in S0:   SLP_S3_L is 1 and SLP_S0_L is 1.
-	 * in S5/G3, the FP MCU should not be running.
-	 */
-	int running = gpio_get_level(GPIO_PCH_SLP_S3_L)
-			&& (gpio_get_level(GPIO_PCH_SLP_S0_L) || broken_slp_s0);
-
-	if (running) { /* S0 */
-		disable_sleep(SLEEP_MASK_AP_RUN);
-		hook_notify(HOOK_CHIPSET_RESUME);
-	} else { /* S0ix/S3 */
-		hook_notify(HOOK_CHIPSET_SUSPEND);
-		enable_sleep(SLEEP_MASK_AP_RUN);
-	}
-}
-DECLARE_DEFERRED(ap_deferred);
-
-/* PCH power state changes */
-void slp_event(enum gpio_signal signal)
-{
-	hook_call_deferred(&ap_deferred_data, 0);
-}
-
 #include "gpio_list.h"
 
-/* SPI devices */
-struct spi_device_t spi_devices[] = {
-	/* Fingerprint sensor (SCLK at 4Mhz) */
-	{ .port = CONFIG_SPI_FP_PORT, .div = 3, .gpio_cs = GPIO_SPI2_NSS }
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-static void configure_fp_sensor_spi(void)
-{
-	/* Configure SPI GPIOs */
-	gpio_config_module(MODULE_SPI_MASTER, 1);
-
-	/* Set all SPI master signal pins to very high speed: B12/13/14/15 */
-	STM32_GPIO_OSPEEDR(GPIO_B) |= 0xff000000;
-
-	/* Enable clocks to SPI2 module (master) */
-	STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
-
-	spi_enable(&spi_devices[0], 1);
-}
-
-/* Initialize board. */
-static void board_init(void)
+static void board_init_transport(void)
 {
 	enum fp_transport_type ret_transport = get_fp_transport_type();
 
-	/* Run until the first S3 entry */
-	disable_sleep(SLEEP_MASK_AP_RUN);
-
-	/* Configure and enable SPI as master for FP sensor */
-	configure_fp_sensor_spi();
-
-	ccprints("TRANSPORT_SEL: %s",
-		fp_transport_type_to_str(ret_transport));
+	ccprints("TRANSPORT_SEL: %s", fp_transport_type_to_str(ret_transport));
 
 	/* Initialize transport based on bootstrap */
 	switch (ret_transport) {
-
 	case FP_TRANSPORT_TYPE_UART:
 		/* Check if CONFIG_USART_HOST_COMMAND is enabled. */
 		if (IS_ENABLED(CONFIG_USART_HOST_COMMAND))
@@ -113,15 +43,6 @@ static void board_init(void)
 
 		/* Disable SPI interrupt to disable SPI transport layer */
 		gpio_disable_interrupt(GPIO_SPI1_NSS);
-
-		/*
-		 * The Zork variants currently have a broken SLP_S0_L signal
-		 * (stuck to 0 in S0). For now, unconditionally ignore it here
-		 * as they are the only UART users and the AP has no S0ix state.
-		 * TODO(b/174695987) once the RW AP firmware has been updated
-		 * on all those machines, remove this workaround.
-		 */
-		broken_slp_s0 = true;
 		break;
 
 	case FP_TRANSPORT_TYPE_SPI:
@@ -134,13 +55,19 @@ static void board_init(void)
 	}
 
 	ccprints("TRANSPORT_SEL: %s",
-		fp_transport_type_to_str(get_fp_transport_type()));
-
-	/* Enable interrupt on PCH power signals */
-	gpio_enable_interrupt(GPIO_PCH_SLP_S3_L);
-	gpio_enable_interrupt(GPIO_PCH_SLP_S0_L);
+		 fp_transport_type_to_str(get_fp_transport_type()));
+}
 
-	/* enable the SPI slave interface if the PCH is up */
-	hook_call_deferred(&ap_deferred_data, 0);
+/* Initialize board. */
+static void board_init(void)
+{
+	/* Run until the first S3 entry.
+	 * No suspend-based power management in RO.
+	 */
+	disable_sleep(SLEEP_MASK_AP_RUN);
+	hook_notify(HOOK_CHIPSET_RESUME);
+	board_init_transport();
+	if (IS_ENABLED(SECTION_IS_RW))
+		board_init_rw();
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/hatch_fp/board.h b/board/hatch_fp/board.h
index 7cd9281ca6..9f2278c47c 100644
--- a/board/hatch_fp/board.h
+++ b/board/hatch_fp/board.h
@@ -247,8 +247,7 @@
 #define TIM_WATCHDOG 16
 
 #include "gpio_signal.h"
-
-void fps_event(enum gpio_signal signal);
+#include "board_rw.h"
 
 #endif /* !__ASSEMBLER__ */
 
diff --git a/board/hatch_fp/board_rw.c b/board/hatch_fp/board_rw.c
new file mode 100644
index 0000000000..40ab5092a7
--- /dev/null
+++ b/board/hatch_fp/board_rw.c
@@ -0,0 +1,100 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "console.h"
+#include "fpsensor_detect.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "registers.h"
+#include "spi.h"
+#include "system.h"
+#include "task.h"
+#include "usart_host_command.h"
+#include "util.h"
+
+#ifndef SECTION_IS_RW
+#error "This file should only be built for RW."
+#endif
+
+/*
+ * Some platforms have a broken SLP_S0_L signal (stuck to 0 in S0)
+ * if set, ignore it and only uses SLP_S3_L for the AP state.
+ */
+static bool broken_slp_s0;
+
+static void ap_deferred(void)
+{
+	/*
+	 * in S3:   SLP_S3_L is 0 and SLP_S0_L is X.
+	 * in S0ix: SLP_S3_L is 1 and SLP_S0_L is 0.
+	 * in S0:   SLP_S3_L is 1 and SLP_S0_L is 1.
+	 * in S5/G3, the FP MCU should not be running.
+	 */
+	int running = gpio_get_level(GPIO_PCH_SLP_S3_L) &&
+		      (gpio_get_level(GPIO_PCH_SLP_S0_L) || broken_slp_s0);
+
+	if (running) { /* S0 */
+		disable_sleep(SLEEP_MASK_AP_RUN);
+		hook_notify(HOOK_CHIPSET_RESUME);
+	} else { /* S0ix/S3 */
+		hook_notify(HOOK_CHIPSET_SUSPEND);
+		enable_sleep(SLEEP_MASK_AP_RUN);
+	}
+}
+DECLARE_DEFERRED(ap_deferred);
+
+/* PCH power state changes */
+void slp_event(enum gpio_signal signal)
+{
+	hook_call_deferred(&ap_deferred_data, 0);
+}
+
+/* SPI devices */
+struct spi_device_t spi_devices[] = {
+	/* Fingerprint sensor (SCLK at 4Mhz) */
+	{ .port = CONFIG_SPI_FP_PORT, .div = 3, .gpio_cs = GPIO_SPI2_NSS }
+};
+const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
+
+static void configure_fp_sensor_spi(void)
+{
+	/* Configure SPI GPIOs */
+	gpio_config_module(MODULE_SPI_MASTER, 1);
+
+	/* Set all SPI master signal pins to very high speed: B12/13/14/15 */
+	STM32_GPIO_OSPEEDR(GPIO_B) |= 0xff000000;
+
+	/* Enable clocks to SPI2 module (master) */
+	STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
+
+	spi_enable(&spi_devices[0], 1);
+}
+
+void board_init_rw(void)
+{
+	enum fp_transport_type ret_transport = get_fp_transport_type();
+
+	if (ret_transport == FP_TRANSPORT_TYPE_UART) {
+		/*
+		 * The Zork variants currently have a broken SLP_S0_L signal
+		 * (stuck to 0 in S0). For now, unconditionally ignore it here
+		 * as they are the only UART users and the AP has no S0ix state.
+		 * TODO(b/174695987) once the RW AP firmware has been updated
+		 * on all those machines, remove this workaround.
+		 */
+		broken_slp_s0 = true;
+	}
+
+	/* Configure and enable SPI as master for FP sensor */
+	configure_fp_sensor_spi();
+
+	/* Enable interrupt on PCH power signals */
+	gpio_enable_interrupt(GPIO_PCH_SLP_S3_L);
+	gpio_enable_interrupt(GPIO_PCH_SLP_S0_L);
+
+	/* enable the SPI slave interface if the PCH is up */
+	hook_call_deferred(&ap_deferred_data, 0);
+}
diff --git a/board/hatch_fp/board_rw.h b/board/hatch_fp/board_rw.h
new file mode 100644
index 0000000000..bcfa061b25
--- /dev/null
+++ b/board/hatch_fp/board_rw.h
@@ -0,0 +1,14 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_BOARD_HATCH_FP_BOARD_RW_H
+#define __CROS_EC_BOARD_HATCH_FP_BOARD_RW_H
+
+void fps_event(enum gpio_signal signal);
+void slp_event(enum gpio_signal signal);
+
+void board_init_rw(void);
+
+#endif /* __CROS_EC_BOARD_HATCH_FP_BOARD_RW_H */
diff --git a/board/hatch_fp/build.mk b/board/hatch_fp/build.mk
index dc6e59eb20..124805d2a9 100644
--- a/board/hatch_fp/build.mk
+++ b/board/hatch_fp/build.mk
@@ -9,6 +9,7 @@ CHIP:=stm32
 CHIP_FAMILY:=stm32f4
 CHIP_VARIANT:=stm32f412
 
+board-rw=board_rw.o
 board-y=board.o
 
 # If we're mocking the sensor detection for testing (so we can test
@@ -16,6 +17,7 @@ board-y=board.o
 # detection.
 ifeq ($(HAS_MOCK_FPSENSOR_DETECT),)
 	board-y+=fpsensor_detect.o
+	board-rw+=fpsensor_detect_rw.o
 endif
 
 # Do not build rsa test because this board uses RSA exponent 3 and the rsa test
diff --git a/board/hatch_fp/fpsensor_detect.c b/board/hatch_fp/fpsensor_detect.c
index 86071bd7f6..638b5fbfe0 100644
--- a/board/hatch_fp/fpsensor_detect.c
+++ b/board/hatch_fp/fpsensor_detect.c
@@ -7,27 +7,6 @@
 #include "gpio.h"
 #include "timer.h"
 
-enum fp_sensor_type get_fp_sensor_type(void)
-{
-	enum fp_sensor_type ret;
-
-	gpio_set_level(GPIO_DIVIDER_HIGHSIDE, 1);
-	usleep(1);
-	switch (gpio_get_level(GPIO_FP_SENSOR_SEL)) {
-	case 0:
-		ret = FP_SENSOR_TYPE_ELAN;
-		break;
-	case 1:
-		ret = FP_SENSOR_TYPE_FPC;
-		break;
-	default:
-		ret = FP_SENSOR_TYPE_UNKNOWN;
-		break;
-	}
-	gpio_set_level(GPIO_DIVIDER_HIGHSIDE, 0);
-	return ret;
-}
-
 enum fp_transport_type get_fp_transport_type(void)
 {
 	enum fp_transport_type ret;
@@ -48,8 +27,3 @@ enum fp_transport_type get_fp_transport_type(void)
 	gpio_set_level(GPIO_DIVIDER_HIGHSIDE, 0);
 	return ret;
 }
-
-enum fp_sensor_spi_select get_fp_sensor_spi_select(void)
-{
-	return FP_SENSOR_SPI_SELECT_PRODUCTION;
-}
diff --git a/board/hatch_fp/fpsensor_detect_rw.c b/board/hatch_fp/fpsensor_detect_rw.c
new file mode 100644
index 0000000000..85ace2c679
--- /dev/null
+++ b/board/hatch_fp/fpsensor_detect_rw.c
@@ -0,0 +1,34 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "fpsensor_detect.h"
+#include "gpio.h"
+#include "timer.h"
+
+enum fp_sensor_type get_fp_sensor_type(void)
+{
+	enum fp_sensor_type ret;
+
+	gpio_set_level(GPIO_DIVIDER_HIGHSIDE, 1);
+	usleep(1);
+	switch (gpio_get_level(GPIO_FP_SENSOR_SEL)) {
+	case 0:
+		ret = FP_SENSOR_TYPE_ELAN;
+		break;
+	case 1:
+		ret = FP_SENSOR_TYPE_FPC;
+		break;
+	default:
+		ret = FP_SENSOR_TYPE_UNKNOWN;
+		break;
+	}
+	gpio_set_level(GPIO_DIVIDER_HIGHSIDE, 0);
+	return ret;
+}
+
+enum fp_sensor_spi_select get_fp_sensor_spi_select(void)
+{
+	return FP_SENSOR_SPI_SELECT_PRODUCTION;
+}
diff --git a/board/hatch_fp/gpio.inc b/board/hatch_fp/gpio.inc
index a5fbeded40..52c8f770f6 100644
--- a/board/hatch_fp/gpio.inc
+++ b/board/hatch_fp/gpio.inc
@@ -5,22 +5,15 @@
  */
 
 /* Interrupts */
-GPIO_INT(FPS_INT,         PIN(A, 0), GPIO_INT_RISING, fps_event)
-GPIO_INT(PCH_SLP_S0_L,    PIN(A, 8), GPIO_INT_BOTH, slp_event)
 GPIO_INT(SPI1_NSS,        PIN(A, 4), GPIO_INPUT, spi_event)
-GPIO_INT(PCH_SLP_S3_L,    PIN(B, 6), GPIO_INT_BOTH, slp_event)
 
 /* Inputs */
-GPIO(FP_SENSOR_SEL,       PIN(B, 0), GPIO_INPUT)
 GPIO(TRANSPORT_SEL,       PIN(B, 1), GPIO_INPUT)
 GPIO(WP,                  PIN(B, 7), GPIO_INPUT)
 
 /* Outputs */
 GPIO(EC_INT_L,            PIN(A, 1),  GPIO_OUT_HIGH)
-GPIO(FP_RST_ODL,          PIN(B,10),  GPIO_OUT_HIGH)
-GPIO(SPI2_NSS,            PIN(B,12),  GPIO_OUT_HIGH)
 GPIO(DIVIDER_HIGHSIDE,    PIN(B, 8),  GPIO_OUT_LOW)
-GPIO(USER_PRES_L,         PIN(B, 9),  GPIO_ODR_HIGH)
 
 /*
  * Unused pins.
@@ -44,10 +37,7 @@ ALTERNATE(PIN_MASK(A, 0x0600), GPIO_ALT_USART,  MODULE_UART, GPIO_PULL_UP)
 ALTERNATE(PIN_MASK(A, 0x000C), GPIO_ALT_USART,  MODULE_UART, GPIO_PULL_UP)
 /* SPI1 slave from the AP: PA4/5/6/7 (CS/CLK/MISO/MOSI) */
 ALTERNATE(PIN_MASK(A, 0x00f0), GPIO_ALT_SPI, MODULE_SPI,  0)
-/*
- * SPI2 master to sensor: PB13/14/15 (CLK/MISO/MOSI)
- * Note that we're not configuring NSS (PB12) here because we have already
- * configured it as a GPIO above and the SPI_MASTER module expects to use it
- * in software NSS management mode, not hardware management mode.
- */
-ALTERNATE(PIN_MASK(B, 0xE000), GPIO_ALT_SPI, MODULE_SPI_MASTER, GPIO_PULL_DOWN)
+
+#ifdef SECTION_IS_RW
+#include "gpio_rw.inc"
+#endif
diff --git a/board/hatch_fp/gpio_rw.inc b/board/hatch_fp/gpio_rw.inc
new file mode 100644
index 0000000000..50d1e76f50
--- /dev/null
+++ b/board/hatch_fp/gpio_rw.inc
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef SECTION_IS_RW
+#error "This file should only be included in RW."
+#endif
+
+/* Interrupts */
+GPIO_INT(FPS_INT,         PIN(A, 0), GPIO_INT_RISING, fps_event)
+GPIO_INT(PCH_SLP_S0_L,    PIN(A, 8), GPIO_INT_BOTH, slp_event)
+GPIO_INT(PCH_SLP_S3_L,    PIN(B, 6), GPIO_INT_BOTH, slp_event)
+
+/* Inputs */
+GPIO(FP_SENSOR_SEL,       PIN(B, 0), GPIO_INPUT)
+
+/* Outputs */
+GPIO(FP_RST_ODL,          PIN(B,10),  GPIO_OUT_HIGH)
+GPIO(SPI2_NSS,            PIN(B,12),  GPIO_OUT_HIGH)
+GPIO(USER_PRES_L,         PIN(B, 9),  GPIO_ODR_HIGH)
+
+/*
+ * SPI2 master to sensor: PB13/14/15 (CLK/MISO/MOSI)
+ * Note that we're not configuring NSS (PB12) here because we have already
+ * configured it as a GPIO above and the SPI_MASTER module expects to use it
+ * in software NSS management mode, not hardware management mode.
+ */
+ALTERNATE(PIN_MASK(B, 0xE000), GPIO_ALT_SPI, MODULE_SPI_MASTER, GPIO_PULL_DOWN)