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author | Scott Collyer <scollyer@google.com> | 2019-08-15 15:01:42 -0700 |
---|---|---|
committer | Commit Bot <commit-bot@chromium.org> | 2019-09-04 02:00:12 +0000 |
commit | 792e0a1de80d97cf9772e998ed84adb262dd12b0 (patch) | |
tree | cfb794c6889f32908128491d036f882e089667c7 /board/helios | |
parent | 6881fa3712de15d4b938dcb330bae7744a6db4bf (diff) | |
download | chrome-ec-792e0a1de80d97cf9772e998ed84adb262dd12b0.tar.gz |
cometlake: Minimize delay for high->low rsmrst passthrough
Hatch designs buffer the PG_EC_RSMRST# signal from the
Silego power good logic through the EC and out EC_PCH_RSMRST# to the
SoC RSMRST# pin. For power off transitions, this should be as fast as
possible, in the ns region if possible. However this time is ~1 msec.
To reduce this delay as much as possible this CL introduces a new
interrupt handler than can be linked to the rsmrst gpio signal. This
interrupt routine handles high->low transitions directly to minimize
the propagation delay. The power_signal_interrupt is then called which
will wake up the chipset task, and low->high transistions continue to
be handled in the power state machine.
BUG=b:132421681
BRANCH=None
TEST=Shorted PP1050_A_PG to ground to force an abrupt power down and
then measured time via scope between PG_EC_RSMRST and
EC_PCH_RSMRST. The delay is reduced from ~1 msec to 45 uSec.
Change-Id: I266138a2e235ce47f3060f8e1f6f9bc6a75073ae
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1757267
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Scott Collyer <scollyer@chromium.org>
Diffstat (limited to 'board/helios')
0 files changed, 0 insertions, 0 deletions