diff options
| author | Wai-Hong Tam <waihong@google.com> | 2021-09-15 16:57:06 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-09-16 23:02:46 +0000 |
| commit | ac36a80c3206c55d365804f561cc89ab1550e99f (patch) | |
| tree | 073ccc519196c923c061501704e8e0fc885125c0 /board/herobrine_npcx9/board.h | |
| parent | e740b27b1dc5b8065b9c618950823c3054ea2bb0 (diff) | |
| download | chrome-ec-ac36a80c3206c55d365804f561cc89ab1550e99f.tar.gz | |
herobrine: Always enable the 5V rail
Prepare the next hardware revision. It has a PPC chip which requires 5V
rail in S5. The 5V rail enable pin should be turned on whenever the
EC is powered.
Since the existing 5V rail enabling is done inside the qcom power
sequence. Trogdor and Herobrine both shares this qcom power sequence.
For Trogdor, this CL moves the 5V rail enabling from the qcom power
sequence to the board level hook.
For Herobrine, this CL updates the GPIO name and modifies the default
level to HIGH. The CONFIG of 5V control should be disabled. As no board
level hook to modify the 5V rail, the 5V is always on.
BRANCH=None
BUG=b:199804198
TEST=Booted both Zephyr and EC-OS images on Herobrine. Checked the 5V
rail is enabled in S0 and S5.
TEST=Booted both Zephyr and EC-OS images on Lazor. Checked the 5V rail
is enabled in S0 and disabled in S5.
Change-Id: Ifa98ee0c4e970dd89952e94cc6a0e289798e6a57
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3163918
Reviewed-by: Keith Short <keithshort@chromium.org>
Diffstat (limited to 'board/herobrine_npcx9/board.h')
| -rw-r--r-- | board/herobrine_npcx9/board.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/herobrine_npcx9/board.h b/board/herobrine_npcx9/board.h index 09c4697672..e0ca39fac0 100644 --- a/board/herobrine_npcx9/board.h +++ b/board/herobrine_npcx9/board.h @@ -68,7 +68,7 @@ #define GPIO_WP_L GPIO_EC_WP_ODL #define GPIO_SWITCHCAP_PG GPIO_SRC_VPH_PWR_PG #define GPIO_ACOK_OD GPIO_CHG_ACOK_OD -#define GPIO_EN_PP5000 GPIO_EN_PP5000_S3 +#define GPIO_EN_PP5000 GPIO_EN_PP5000_S5 #define GPIO_POWER_GOOD GPIO_MB_POWER_GOOD #define GPIO_EC_INT_L GPIO_AP_EC_INT_L #define GPIO_DP_HOT_PLUG_DET GPIO_DP_HOT_PLUG_DET_R |