diff options
author | Todd Broch <tbroch@chromium.org> | 2014-09-10 12:22:45 -0700 |
---|---|---|
committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2014-09-12 03:39:20 +0000 |
commit | dd0524e385449960d83925eea6aa8755df92bc4b (patch) | |
tree | 6c71539fa55825ed6f2c08fb4fa22bc167bc7339 /board/hoho/board.c | |
parent | f53f949ac66d55f5c06bef0a916a3e4641f6636a (diff) | |
download | chrome-ec-dd0524e385449960d83925eea6aa8755df92bc4b.tar.gz |
hoho: Enable spi2 master for comm with external flash.
BRANCH=none
BUG=chrome-os-partner:31192
TEST=manual, from console,
> spi_flashinfo
Manufacturer ID: ef
Device ID: 40 14
Unique ID: dc 63 a0 00 db 57 56 28
Capacity: 1024 MB
> spi_flashread 0 64
Reading 64 bytes from 0x0...
00: 00 b8 00 00 8e d0 8e d8 8e c0 bc 00 80 b8 94 41
10: 8e d8 be 00 00 bf 00 1a b9 ee 1a 2b cf d1 e9 f3
20: a5 b8 00 00 8e d8 fd b8 55 55 bf fe 7f b9 00 04
30: f3 ab fc bd 00 00 ea e0 00 02 40 c3 56 96 92 85
Change-Id: I9d8aade3fb99f4a9d85afceb153a350750382a81
Signed-off-by: Todd Broch <tbroch@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217531
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Diffstat (limited to 'board/hoho/board.c')
-rw-r--r-- | board/hoho/board.c | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/board/hoho/board.c b/board/hoho/board.c index b0e3a7d37b..c30cbfd3a2 100644 --- a/board/hoho/board.c +++ b/board/hoho/board.c @@ -26,6 +26,46 @@ void board_config_pre_init(void) STM32_SYSCFG_CFGR1 |= (1 << 9) | (1 << 10);/* Remap USART1 RX/TX DMA */ } +#ifdef CONFIG_SPI_FLASH + +static void board_init_spi2(void) +{ + /* Remap SPI2 to DMA channels 6 and 7 */ + STM32_SYSCFG_CFGR1 |= (1 << 24); + + /* Set pin NSS to general purpose output mode (01b). */ + /* Set pins SCK, MISO, and MOSI to alternate function (10b). */ + STM32_GPIO_MODER(GPIO_B) &= ~0xff000000; + STM32_GPIO_MODER(GPIO_B) |= 0xa9000000; + + /* Set all four pins to alternate function 0 */ + STM32_GPIO_AFRH(GPIO_B) &= ~(0xffff0000); + + /* Set all four pins to output push-pull */ + STM32_GPIO_OTYPER(GPIO_B) &= ~(0xf000); + + /* Set pullup on NSS */ + STM32_GPIO_PUPDR(GPIO_B) |= 0x1000000; + + /* Set all four pins to high speed */ + STM32_GPIO_OSPEEDR(GPIO_B) |= 0xff000000; + + /* Reset SPI2 */ + STM32_RCC_APB1RSTR |= (1 << 14); + STM32_RCC_APB1RSTR &= ~(1 << 14); + + /* Enable clocks to SPI2 module */ + STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2; +} + +/* Initialize board. */ +static void board_init(void) +{ + board_init_spi2(); +} +DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); +#endif /* CONFIG_SPI_FLASH */ + /* ADC channels */ const struct adc_t adc_channels[] = { /* USB PD CC lines sensing. Converted to mV (3300mV/4096). */ |