diff options
| author | Gwendal Grignou <gwendal@chromium.org> | 2019-03-11 15:57:52 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2019-03-26 04:42:55 -0700 |
| commit | bb266fc26fc05d4ab22de6ad7bce5b477c9f9140 (patch) | |
| tree | f6ada087f62246c3a9547e649ac8846b0ed6d5ab /board/hoho/board.c | |
| parent | 0bfc511527cf2aebfa163c63a1d028419ca0b0c3 (diff) | |
| download | chrome-ec-bb266fc26fc05d4ab22de6ad7bce5b477c9f9140.tar.gz | |
common: replace 1 << digits, with BIT(digits)
Requested for linux integration, use BIT instead of 1 <<
First step replace bit operation with operand containing only digits.
Fix an error in motion_lid try to set bit 31 of a signed integer.
BUG=None
BRANCH=None
TEST=compile
Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1518659
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Diffstat (limited to 'board/hoho/board.c')
| -rw-r--r-- | board/hoho/board.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/board/hoho/board.c b/board/hoho/board.c index e6258f19b4..69ef58f59c 100644 --- a/board/hoho/board.c +++ b/board/hoho/board.c @@ -97,9 +97,9 @@ void hpd_event(enum gpio_signal signal) void board_config_pre_init(void) { /* enable SYSCFG clock */ - STM32_RCC_APB2ENR |= 1 << 0; + STM32_RCC_APB2ENR |= BIT(0); /* Remap USART DMA to match the USART driver */ - STM32_SYSCFG_CFGR1 |= (1 << 9) | (1 << 10);/* Remap USART1 RX/TX DMA */ + STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10);/* Remap USART1 RX/TX DMA */ } #ifdef CONFIG_SPI_FLASH @@ -107,7 +107,7 @@ void board_config_pre_init(void) static void board_init_spi2(void) { /* Remap SPI2 to DMA channels 6 and 7 */ - STM32_SYSCFG_CFGR1 |= (1 << 24); + STM32_SYSCFG_CFGR1 |= BIT(24); /* Set pin NSS to general purpose output mode (01b). */ /* Set pins SCK, MISO, and MOSI to alternate function (10b). */ @@ -127,8 +127,8 @@ static void board_init_spi2(void) STM32_GPIO_OSPEEDR(GPIO_B) |= 0xff000000; /* Reset SPI2 */ - STM32_RCC_APB1RSTR |= (1 << 14); - STM32_RCC_APB1RSTR &= ~(1 << 14); + STM32_RCC_APB1RSTR |= BIT(14); + STM32_RCC_APB1RSTR &= ~BIT(14); /* Enable clocks to SPI2 module */ STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2; |