diff options
author | Todd Broch <tbroch@chromium.org> | 2014-09-11 15:42:38 -0700 |
---|---|---|
committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2014-09-23 06:28:48 +0000 |
commit | 53b6a345c8f7fecd8c8f8ea1e23870308dafdf44 (patch) | |
tree | 7c6f5d55c66fc3f42cad7c64f9ff6be9efb36204 /board/hoho/usb_pd_config.h | |
parent | 4fda01ca91f8e4c50ecddb904b4794df40e4d49f (diff) | |
download | chrome-ec-53b6a345c8f7fecd8c8f8ea1e23870308dafdf44.tar.gz |
hoho: Enable USB PD support.
CL to allow hoho to receive initial USB PD communication (source
capabilities payload).
BRANCH=none
BUG=chrome-os-partner:31192
TEST=manual,
When attaching hoho to fruitpie and configured via
'pd dualrole source'
I see on hoho side:
--- UART initialized after reboot ---
[Reset cause: reset-pin power-on]
[Image: RO, hoho_v1.1.2213-2bf6a29-dirty 2014-09-15 12:10:22 tbroch@brisket.mtv.corp.google.com]
[0.000466 Inits done]
C0 st2
Console is enabled; type HELP for help.
> [0.250678 USB PD initialized]
C0 st3
[0.264629 PD TMOUT RX 1/1]
RX ERR (-1)
Request [1] 5V 3000mA
C0 st4
C0 st5
C0 st6
> pd 0 state
Port C0, Enabled - Role: SNK Polarity: CC2 State: SNK_READY
Change-Id: Ic5871946425f0ff12d717fbbbbb9e81c6b67cc6f
Signed-off-by: Todd Broch <tbroch@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217977
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Diffstat (limited to 'board/hoho/usb_pd_config.h')
-rw-r--r-- | board/hoho/usb_pd_config.h | 140 |
1 files changed, 140 insertions, 0 deletions
diff --git a/board/hoho/usb_pd_config.h b/board/hoho/usb_pd_config.h new file mode 100644 index 0000000000..4abb3e8d51 --- /dev/null +++ b/board/hoho/usb_pd_config.h @@ -0,0 +1,140 @@ +/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* USB Power delivery board configuration */ + +#ifndef __USB_PD_CONFIG_H +#define __USB_PD_CONFIG_H + +/* Port and task configuration */ +#define PD_PORT_COUNT 1 +#define PORT_TO_TASK_ID(port) TASK_ID_PD +#define TASK_ID_TO_PORT(id) 0 + +/* Timer selection for baseband PD communication */ +#define TIM_CLOCK_PD_TX_C0 17 +#define TIM_CLOCK_PD_RX_C0 1 + +#define TIM_CLOCK_PD_TX(p) TIM_CLOCK_PD_TX_C0 +#define TIM_CLOCK_PD_RX(p) TIM_CLOCK_PD_RX_C0 + +/* Timer channel */ +#define TIM_RX_CCR_C0 1 + +/* RX timer capture/compare register */ +#define TIM_CCR_C0 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C0, TIM_RX_CCR_C0)) +#define TIM_RX_CCR_REG(p) TIM_CCR_C0 + +/* TX and RX timer register */ +#define TIM_REG_TX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_TX_C0)) +#define TIM_REG_RX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_RX_C0)) +#define TIM_REG_TX(p) TIM_REG_TX_C0 +#define TIM_REG_RX(p) TIM_REG_RX_C0 + +/* use the hardware accelerator for CRC */ +#define CONFIG_HW_CRC + +/* TX is using SPI1 on PB3-4 */ +#define SPI_REGS(p) STM32_SPI1_REGS + +static inline void spi_enable_clock(int port) +{ + STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1; +} + +/* SPI1_TX no remap needed */ +#define DMAC_SPI_TX(p) STM32_DMAC_CH3 + +/* RX is using COMP1 triggering TIM1 CH1 */ +#define CMP1OUTSEL STM32_COMP_CMP1OUTSEL_TIM1_IC1 +#define CMP2OUTSEL 0 + +#define TIM_CCR_IDX(p) TIM_RX_CCR_C0 +#define TIM_CCR_CS 1 +#define EXTI_COMP_MASK(p) (1 << 21) +#define IRQ_COMP STM32_IRQ_COMP +/* triggers packet detection on comparator falling edge */ +#define EXTI_XTSR STM32_EXTI_FTSR + +/* TIM1_CH1 no remap needed */ +#define DMAC_TIM_RX(p) STM32_DMAC_CH2 + +/* the pins used for communication need to be hi-speed */ +static inline void pd_set_pins_speed(int port) +{ + /* 40 Mhz pin speed on TX_EN (PA15) */ + STM32_GPIO_OSPEEDR(GPIO_A) |= 0xC0000000; + /* 40 MHz pin speed on SPI CLK/MOSI (PB3/4) TIM17_CH1 (PB9) */ + STM32_GPIO_OSPEEDR(GPIO_B) |= 0x000C03C0; +} + +/* Reset SPI peripheral used for TX */ +static inline void pd_tx_spi_reset(int port) +{ + /* Reset SPI1 */ + STM32_RCC_APB2RSTR |= (1 << 12); + STM32_RCC_APB2RSTR &= ~(1 << 12); +} + +/* Drive the CC line from the TX block */ +static inline void pd_tx_enable(int port, int polarity) +{ + /* PB4 is SPI1_MISO */ + gpio_set_alternate_function(GPIO_B, 0x0010, 0); + + gpio_set_level(GPIO_PD_CC1_TX_EN, 1); +} + +/* Put the TX driver in Hi-Z state */ +static inline void pd_tx_disable(int port, int polarity) +{ + /* output low on SPI TX (PB4) to disable the FET */ + STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B) + & ~(3 << (2*4))) + | (1 << (2*4)); + /* put the low level reference in Hi-Z */ + gpio_set_level(GPIO_PD_CC1_TX_EN, 0); +} + +static inline void pd_select_polarity(int port, int polarity) +{ + /* + * use the right comparator : CC1 -> PA1 (COMP1 INP) + * use VrefInt / 2 as INM (about 600mV) + */ + STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK) + | STM32_COMP_CMP1EN | STM32_COMP_CMP1INSEL_VREF12; +} + +/* Initialize pins used for TX and put them in Hi-Z */ +static inline void pd_tx_init(void) +{ + gpio_config_module(MODULE_USB_PD, 1); +} + +static inline void pd_set_host_mode(int port, int enable) {} + +static inline int pd_adc_read(int port, int cc) +{ + return adc_read_channel(ADC_CH_CC1_PD); +} + +static inline int pd_snk_is_vbus_provided(int port) +{ + return 1; +} + +/* 3.0A DFP : no-connect voltage is 2.45V */ +#define PD_SRC_VNC 2450 /* mV */ + +/* UFP-side : threshold for DFP connection detection */ +#define PD_SNK_VA 250 /* mV */ + +/* we are acting only as a sink */ +#define PD_DEFAULT_STATE PD_STATE_SNK_DISCONNECTED + +/* delay necessary for the voltage transition on the power supply */ +#define PD_POWER_SUPPLY_TRANSITION_DELAY 50000 /* us */ +#endif /* __USB_PD_CONFIG_H */ |