diff options
author | Steven Jian <steven.jian@intel.com> | 2015-04-01 01:25:42 +0800 |
---|---|---|
committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-05-27 03:58:16 +0000 |
commit | 937cc8a64e5971def21303e7a19a4ad9553e0ace (patch) | |
tree | 321543152e0c4d61e686ca7b92edd0d027bb168b /board/hoho | |
parent | e216906c9327655d71b8758b7f11c2f744e55018 (diff) | |
download | chrome-ec-937cc8a64e5971def21303e7a19a4ad9553e0ace.tar.gz |
mec1322: Simplify GPIO lists
Our existing GPIO macros use port# / gpio#, but the concept of different
GPIO ports does not exist on the mec1322. Therefore, add new GPIO macros
for chips which do not have distinct GPIO ports.
BUG=None
BRANCH=None
TEST=make buildall -j
Change-Id: Ibda97c6563ad447d16dab39ecadab43ccb25174b
Signed-off-by: Steven Jian <steven.jian@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/262841
Reviewed-by: Anton Staaf <robotboy@chromium.org>
Diffstat (limited to 'board/hoho')
-rw-r--r-- | board/hoho/gpio.inc | 38 |
1 files changed, 19 insertions, 19 deletions
diff --git a/board/hoho/gpio.inc b/board/hoho/gpio.inc index 72c8b93b22..787eaf7e90 100644 --- a/board/hoho/gpio.inc +++ b/board/hoho/gpio.inc @@ -5,30 +5,30 @@ * found in the LICENSE file. */ -GPIO_INT(DP_HPD, A, 0, GPIO_INT_BOTH, hpd_event) +GPIO_INT(DP_HPD, PIN(A, 0), GPIO_INT_BOTH, hpd_event) -GPIO(USB_C_CC1_PD, A, 1, GPIO_ANALOG) -GPIO(STM_READY, A, 2, GPIO_OUT_LOW) /* factory test only */ -GPIO(MCDP_RESET_L, A, 3, GPIO_OUT_HIGH) -GPIO(PD_DAC_REF, A, 4, GPIO_ANALOG) +GPIO(USB_C_CC1_PD, PIN(A, 1), GPIO_ANALOG) +GPIO(STM_READY, PIN(A, 2), GPIO_OUT_LOW) /* factory test only */ +GPIO(MCDP_RESET_L, PIN(A, 3), GPIO_OUT_HIGH) +GPIO(PD_DAC_REF, PIN(A, 4), GPIO_ANALOG) -GPIO(MCDP_READY, A, 7, GPIO_OUT_LOW) /* factory test only */ -GPIO(PD_SBU_ENABLE, A, 8, GPIO_OUT_LOW) -GPIO(USB_DM, A, 11, GPIO_ANALOG) -GPIO(USB_DP, A, 12, GPIO_ANALOG) -GPIO(PD_CC1_TX_EN, A, 15, GPIO_OUT_LOW) +GPIO(MCDP_READY, PIN(A, 7), GPIO_OUT_LOW) /* factory test only */ +GPIO(PD_SBU_ENABLE, PIN(A, 8), GPIO_OUT_LOW) +GPIO(USB_DM, PIN(A, 11), GPIO_ANALOG) +GPIO(USB_DP, PIN(A, 12), GPIO_ANALOG) +GPIO(PD_CC1_TX_EN, PIN(A, 15), GPIO_OUT_LOW) -GPIO(MCDP_GPIO1, B, 0, GPIO_INPUT) -GPIO(MCDP_CONFIG1, B, 1, GPIO_INPUT) -GPIO(PD_MCDP_SPI_WP_L, B, 2, GPIO_OUT_LOW) -GPIO(PD_CC1_TX_DATA, B, 4, GPIO_OUT_LOW) -GPIO(PD_MCDP_SPI_CS_L, B, 12, GPIO_INPUT) +GPIO(MCDP_GPIO1, PIN(B, 0), GPIO_INPUT) +GPIO(MCDP_CONFIG1, PIN(B, 1), GPIO_INPUT) +GPIO(PD_MCDP_SPI_WP_L, PIN(B, 2), GPIO_OUT_LOW) +GPIO(PD_CC1_TX_DATA, PIN(B, 4), GPIO_OUT_LOW) +GPIO(PD_MCDP_SPI_CS_L, PIN(B, 12), GPIO_INPUT) /* Unimplemented signals which we need to emulate for now */ UNIMPLEMENTED(ENTERING_RW) UNIMPLEMENTED(WP_L) -ALTERNATE(B, 0x0008, 0, MODULE_USB_PD, 0) /* SPI1: SCK(PB3) */ -ALTERNATE(B, 0x0200, 2, MODULE_USB_PD, 0) /* TIM17_CH1: PB9 */ -ALTERNATE(A, 0x0600, 1, MODULE_UART, GPIO_PULL_UP) /* USART1: PA9/PA10 */ -ALTERNATE(B, 0x0C00, 4, MODULE_UART, GPIO_PULL_UP) /* USART3: PB10/PB11 */ +ALTERNATE(PIN_MASK(B, 0x0008), 0, MODULE_USB_PD, 0) /* SPI1: SCK(PB3) */ +ALTERNATE(PIN_MASK(B, 0x0200), 2, MODULE_USB_PD, 0) /* TIM17_CH1: PB9 */ +ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART, GPIO_PULL_UP) /* USART1: PA9/PA10 */ +ALTERNATE(PIN_MASK(B, 0x0C00), 4, MODULE_UART, GPIO_PULL_UP) /* USART3: PB10/PB11 */ |