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| author | Vijay Hiremath <vijay.p.hiremath@intel.com> | 2018-03-22 04:55:51 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-03-24 07:32:29 -0700 |
| commit | 3bd4e0de5edc6f62eda8739d31816b5b29d1979b (patch) | |
| tree | d6cc7049652e5fc41b765e0708e8722e4ca7bd24 /board/it83xx_evb | |
| parent | f59290878e5fcd99add71aec74baea7d1e3f0297 (diff) | |
| download | chrome-ec-3bd4e0de5edc6f62eda8739d31816b5b29d1979b.tar.gz | |
Code cleanup: Rename GPIO PCH_RCIN_L to SYS_RESET_L
Renamed GPIO PCH_RCIN_L to SYS_RESET_L so that all the Intel
chipset variants have same GPIO name for doing SOC internal reset.
BUG=b:72426192
BRANCH=none
TEST=make buildall -j
Change-Id: I931ce136743fa928dd7cf6f005c912db3b2da893
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/974241
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Diffstat (limited to 'board/it83xx_evb')
| -rw-r--r-- | board/it83xx_evb/gpio.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/it83xx_evb/gpio.inc b/board/it83xx_evb/gpio.inc index 96d362e4bd..c8a9c099ab 100644 --- a/board/it83xx_evb/gpio.inc +++ b/board/it83xx_evb/gpio.inc @@ -35,7 +35,7 @@ GPIO(USBPD_PORTA_VBUS_DROP, PIN(E, 5), GPIO_OUT_LOW) GPIO(PCH_SMI_L, PIN(D, 3), GPIO_OUT_HIGH) GPIO(PCH_SCI_L, PIN(D, 4), GPIO_OUT_HIGH) GPIO(GATE_A20_H, PIN(B, 5), GPIO_OUT_HIGH) -GPIO(PCH_RCIN_L, PIN(B, 6), GPIO_OUT_HIGH) +GPIO(SYS_RESET_L, PIN(B, 6), GPIO_OUT_HIGH) GPIO(LPC_CLKRUN_L, PIN(H, 0), GPIO_OUT_LOW) GPIO(PCH_WAKE_L, PIN(B, 7), GPIO_ODR_HIGH) /* Wake signal from EC to PCH */ |