diff options
author | Dino Li <dino.li@ite.com.tw> | 2016-05-03 13:35:51 +0800 |
---|---|---|
committer | chrome-bot <chrome-bot@chromium.org> | 2016-05-03 22:00:49 -0700 |
commit | 32bf8ecb773e0c6da80ef06b26375742fa287704 (patch) | |
tree | 60d95ebe40ac81399a0df7b49f52a005c93f58e4 /board/it83xx_evb | |
parent | e83c06bf90f89ea8c160c9f88b166d0c2e0a982d (diff) | |
download | chrome-ec-32bf8ecb773e0c6da80ef06b26375742fa287704.tar.gz |
board: rename it8380dev to it83xx_evb
Unified board name for IT83-series.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST="make BOARD=it83xx_evb -j" and "make buildall -j"
Change-Id: Ic96d0132fb31fcc8715d0dd810f8bd340035a640
Reviewed-on: https://chromium-review.googlesource.com/341843
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'board/it83xx_evb')
l--------- | board/it83xx_evb/Makefile | 1 | ||||
-rw-r--r-- | board/it83xx_evb/board.c | 244 | ||||
-rw-r--r-- | board/it83xx_evb/board.h | 121 | ||||
-rw-r--r-- | board/it83xx_evb/build.mk | 11 | ||||
-rw-r--r-- | board/it83xx_evb/ec.tasklist | 24 | ||||
-rw-r--r-- | board/it83xx_evb/gpio.inc | 78 |
6 files changed, 479 insertions, 0 deletions
diff --git a/board/it83xx_evb/Makefile b/board/it83xx_evb/Makefile new file mode 120000 index 0000000000..94aaae2c4d --- /dev/null +++ b/board/it83xx_evb/Makefile @@ -0,0 +1 @@ +../../Makefile
\ No newline at end of file diff --git a/board/it83xx_evb/board.c b/board/it83xx_evb/board.c new file mode 100644 index 0000000000..b63f6b9dcb --- /dev/null +++ b/board/it83xx_evb/board.c @@ -0,0 +1,244 @@ +/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ +/* IT8380 development board configuration */ + +#include "adc.h" +#include "adc_chip.h" +#include "clock.h" +#include "common.h" +#include "console.h" +#include "ec2i_chip.h" +#include "fan.h" +#include "gpio.h" +#include "hooks.h" +#include "i2c.h" +#include "intc.h" +#include "keyboard_scan.h" +#include "lid_switch.h" +#include "lpc.h" +#include "power_button.h" +#include "pwm.h" +#include "pwm_chip.h" +#include "registers.h" +#include "spi.h" +#include "switch.h" +#include "system.h" +#include "task.h" +#include "timer.h" +#include "uart.h" +#include "util.h" + +#include "gpio_list.h" + +/* + * PWM channels. Must be in the exactly same order as in enum pwm_channel. + * There total three 16 bits clock prescaler registers for all pwm channels, + * so use the same frequency and prescaler register setting is required if + * number of pwm channel greater than three. + */ +const struct pwm_t pwm_channels[] = { + {7, 0, 30000, PWM_PRESCALER_C4}, + {1, PWM_CONFIG_ACTIVE_LOW, 1000, PWM_PRESCALER_C6}, + {2, 0, 200, PWM_PRESCALER_C7}, + {3, PWM_CONFIG_ACTIVE_LOW, 1000, PWM_PRESCALER_C6}, + {4, 0, 30000, PWM_PRESCALER_C4}, + {5, PWM_CONFIG_ACTIVE_LOW, 200, PWM_PRESCALER_C7}, + {0, PWM_CONFIG_ACTIVE_LOW, 1000, PWM_PRESCALER_C6}, +}; + +BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); + +const struct fan_t fans[] = { + {.flags = FAN_USE_RPM_MODE, + .rpm_min = 1500, + .rpm_start = 1500, + .rpm_max = 6500, + /* + * index of pwm_channels, not pwm output channel. + * pwm output channel is member "channel" of pwm_t. + */ + .ch = 0, + .pgood_gpio = -1, + .enable_gpio = -1, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(fans) == CONFIG_FANS); + +/* + * PWM HW channelx binding tachometer channelx for fan control. + * Four tachometer input pins but two tachometer modules only, + * so always binding [TACH_CH_TACH0A | TACH_CH_TACH0B] and/or + * [TACH_CH_TACH1A | TACH_CH_TACH1B] + */ +const struct fan_tach_t fan_tach[] = { + {TACH_CH_NULL, -1, -1, -1}, + {TACH_CH_NULL, -1, -1, -1}, + {TACH_CH_NULL, -1, -1, -1}, + {TACH_CH_NULL, -1, -1, -1}, + {TACH_CH_NULL, -1, -1, -1}, + {TACH_CH_NULL, -1, -1, -1}, + {TACH_CH_NULL, -1, -1, -1}, + {TACH_CH_TACH0A, 2, 50, 30}, +}; +BUILD_ASSERT(ARRAY_SIZE(fan_tach) == PWM_HW_CH_TOTAL); + +/* PNPCFG settings */ +const struct ec2i_t pnpcfg_settings[] = { + /* Select logical device 06h(keyboard) */ + {HOST_INDEX_LDN, LDN_KBC_KEYBOARD}, + /* Set IRQ=01h for logical device */ + {HOST_INDEX_IRQNUMX, 0x01}, + /* Enable logical device */ + {HOST_INDEX_LDA, 0x01}, + + /* Select logical device 05h(mouse) */ + {HOST_INDEX_LDN, LDN_KBC_MOUSE}, + /* Set IRQ=0Ch for logical device */ + {HOST_INDEX_IRQNUMX, 0x0C}, + /* Enable logical device */ + {HOST_INDEX_LDA, 0x01}, + + /* Select logical device 11h(PM1 ACPI) */ + {HOST_INDEX_LDN, LDN_PMC1}, + /* Set IRQ=00h for logical device */ + {HOST_INDEX_IRQNUMX, 0x00}, + /* Enable logical device */ + {HOST_INDEX_LDA, 0x01}, + + /* Select logical device 12h(PM2) */ + {HOST_INDEX_LDN, LDN_PMC2}, + /* I/O Port Base Address 200h/204h */ + {HOST_INDEX_IOBAD0_MSB, 0x02}, + {HOST_INDEX_IOBAD0_LSB, 0x00}, + {HOST_INDEX_IOBAD1_MSB, 0x02}, + {HOST_INDEX_IOBAD1_LSB, 0x04}, + /* Set IRQ=00h for logical device */ + {HOST_INDEX_IRQNUMX, 0x00}, + /* Enable logical device */ + {HOST_INDEX_LDA, 0x01}, + + /* Select logical device 0Fh(SMFI) */ + {HOST_INDEX_LDN, LDN_SMFI}, + /* H2RAM LPC I/O cycle Dxxx */ + {HOST_INDEX_DSLDC6, 0x00}, + /* Enable H2RAM LPC I/O cycle */ + {HOST_INDEX_DSLDC7, 0x01}, + /* Enable logical device */ + {HOST_INDEX_LDA, 0x01}, + + /* Select logical device 17h(PM3) */ + {HOST_INDEX_LDN, LDN_PMC3}, + /* I/O Port Base Address 80h */ + {HOST_INDEX_IOBAD0_MSB, 0x00}, + {HOST_INDEX_IOBAD0_LSB, 0x80}, + {HOST_INDEX_IOBAD1_MSB, 0x00}, + {HOST_INDEX_IOBAD1_LSB, 0x00}, + /* Set IRQ=00h for logical device */ + {HOST_INDEX_IRQNUMX, 0x00}, + /* Enable logical device */ + {HOST_INDEX_LDA, 0x01}, + /* Select logical device 10h(RTCT) */ + {HOST_INDEX_LDN, LDN_RTCT}, + /* P80L Begin Index */ + {HOST_INDEX_DSLDC4, P80L_P80LB}, + /* P80L End Index */ + {HOST_INDEX_DSLDC5, P80L_P80LE}, + /* P80L Current Index */ + {HOST_INDEX_DSLDC6, P80L_P80LC}, +#ifdef CONFIG_UART_HOST + /* Select logical device 2h(UART2) */ + {HOST_INDEX_LDN, LDN_UART2}, + /* + * I/O port base address is 2F8h. + * Host can use LPC I/O port 0x2F8 ~ 0x2FF to access UART2. + * See specification 7.24.4 for more detial. + */ + {HOST_INDEX_IOBAD0_MSB, 0x02}, + {HOST_INDEX_IOBAD0_LSB, 0xF8}, + /* IRQ number is 3 */ + {HOST_INDEX_IRQNUMX, 0x03}, + /* + * Interrupt Request Type Select + * bit1, 0: IRQ request is buffered and applied to SERIRQ. + * 1: IRQ request is inverted before being applied to SERIRQ. + * bit0, 0: Edge triggered mode. + * 1: Level triggered mode. + */ + {HOST_INDEX_IRQTP, 0x02}, + /* Enable logical device */ + {HOST_INDEX_LDA, 0x01}, +#endif +}; +BUILD_ASSERT(ARRAY_SIZE(pnpcfg_settings) == EC2I_SETTING_COUNT); + +/* Initialize board. */ +static void board_init(void) +{ +} +DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); + +/* ADC channels. Must be in the exactly same order as in enum adc_channel. */ +const struct adc_t adc_channels[] = { + /* Convert to mV (3000mV/1024). */ + {"adc_ch0", 3000, 1024, 0, 0}, + {"adc_ch1", 3000, 1024, 0, 1}, + {"adc_ch2", 3000, 1024, 0, 2}, + {"adc_ch3", 3000, 1024, 0, 3}, + {"adc_ch4", 3000, 1024, 0, 4}, + {"adc_ch5", 3000, 1024, 0, 5}, + {"adc_ch6", 3000, 1024, 0, 6}, + {"adc_ch7", 3000, 1024, 0, 7}, +}; +BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); + +/* Keyboard scan setting */ +struct keyboard_scan_config keyscan_config = { + .output_settle_us = 35, + .debounce_down_us = 5 * MSEC, + .debounce_up_us = 40 * MSEC, + .scan_period_us = 3 * MSEC, + .min_post_scan_delay_us = 1000, + .poll_timeout_us = 100 * MSEC, + .actual_key_mask = { + 0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, + 0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca /* full set */ + }, +}; + +/* + * I2C channels (A, B, and C) are using the same timing registers (00h~07h) + * at default. + * In order to set frequency independently for each channels, + * We use timing registers 09h~0Bh, and the supported frequency will be: + * 50KHz, 100KHz, 400KHz, or 1MHz. + * I2C channels (D, E and F) can be set different frequency on different ports. + * The I2C(D/E/F) frequency depend on the frequency of SMBus Module and + * the individual prescale register. + * The frequency of SMBus module is 24MHz on default. + * The allowed range of I2C(D/E/F) frequency is as following setting. + * SMBus Module Freq = PLL_CLOCK / ((IT83XX_ECPM_SCDCR2 & 0x0F) + 1) + * (SMBus Module Freq / 510) <= I2C Freq <= (SMBus Module Freq / 8) + * Channel D has multi-function and can be used as UART interface. + * Channel F is reserved for EC debug. + */ + +/* I2C ports */ +const struct i2c_port_t i2c_ports[] = { + {"battery", IT83XX_I2C_CH_C, 100, GPIO_I2C_C_SCL, GPIO_I2C_C_SDA}, + {"evb-1", IT83XX_I2C_CH_A, 100, GPIO_I2C_A_SCL, GPIO_I2C_A_SDA}, + {"evb-2", IT83XX_I2C_CH_B, 100, GPIO_I2C_B_SCL, GPIO_I2C_B_SDA}, +#ifndef CONFIG_UART_HOST + {"opt-3", IT83XX_I2C_CH_D, 100, GPIO_I2C_D_SCL, GPIO_I2C_D_SDA}, +#endif + {"opt-4", IT83XX_I2C_CH_E, 100, GPIO_I2C_E_SCL, GPIO_I2C_E_SDA}, +}; + +const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); + +/* SPI devices */ +const struct spi_device_t spi_devices[] = { + { CONFIG_SPI_FLASH_PORT, 0, -1}, +}; +const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); diff --git a/board/it83xx_evb/board.h b/board/it83xx_evb/board.h new file mode 100644 index 0000000000..b2cf093968 --- /dev/null +++ b/board/it83xx_evb/board.h @@ -0,0 +1,121 @@ +/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* IT8380 development board configuration */ + +#ifndef __CROS_EC_BOARD_H +#define __CROS_EC_BOARD_H + +/* Optional features */ +#define CONFIG_BATTERY_SMART +#define CONFIG_BOARD_VERSION +#define CONFIG_FANS 1 +#define CONFIG_I2C +#define CONFIG_I2C_MASTER +#define CONFIG_IT83XX_LPC_ACCESS_INT +#define CONFIG_IT83XX_SMCLK2_ON_GPC7 +#define CONFIG_KEYBOARD_BOARD_CONFIG +#define CONFIG_KEYBOARD_PROTOCOL_8042 +#define CONFIG_LOW_POWER_IDLE +#define CONFIG_PECI_TJMAX 100 +#define CONFIG_POWER_BUTTON +/* Use CS0 of SSPI */ +#define CONFIG_SPI_FLASH_PORT 0 +#define CONFIG_UART_HOST + +/* Optional console commands */ +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_SCRATCHPAD +#define CONFIG_CMD_STACKOVERFLOW + +/* Debug */ +#undef CONFIG_CMD_FORCETIME +#undef CONFIG_HOOK_DEBUG +#undef CONFIG_KEYBOARD_DEBUG +#undef CONFIG_UART_TX_BUF_SIZE +#define CONFIG_UART_TX_BUF_SIZE 4096 + +#ifndef __ASSEMBLER__ + +#include "registers.h" + +#define I2C_PORT_CHARGER IT83XX_I2C_CH_C +#define I2C_PORT_BATTERY IT83XX_I2C_CH_C + +#include "gpio_signal.h" + +enum pwm_channel { + PWM_CH_FAN, + PWM_CH_1, + PWM_CH_2, + PWM_CH_3, + PWM_CH_4, + PWM_CH_5, + PWM_CH_7, + + /* Number of PWM channels */ + PWM_CH_COUNT +}; + +enum adc_channel { + ADC_CH_0, + ADC_CH_1, + ADC_CH_2, + ADC_CH_3, + ADC_CH_4, + ADC_CH_5, + ADC_CH_6, + ADC_CH_7, + + /* Number of ADC channels */ + ADC_CH_COUNT +}; + +enum ec2i_setting { + EC2I_SET_KB_LDN, + EC2I_SET_KB_IRQ, + EC2I_SET_KB_ENABLE, + EC2I_SET_MOUSE_LDN, + EC2I_SET_MOUSE_IRQ, + EC2I_SET_MOUSE_ENABLE, + EC2I_SET_PMC1_LDN, + EC2I_SET_PMC1_IRQ, + EC2I_SET_PMC1_ENABLE, + EC2I_SET_PMC2_LDN, + EC2I_SET_PMC2_BASE0_MSB, + EC2I_SET_PMC2_BASE0_LSB, + EC2I_SET_PMC2_BASE1_MSB, + EC2I_SET_PMC2_BASE1_LSB, + EC2I_SET_PMC2_IRQ, + EC2I_SET_PMC2_ENABLE, + EC2I_SET_SMFI_LDN, + EC2I_SET_SMFI_H2RAM_IO_BASE, + EC2I_SET_SMFI_H2RAM_MAP_LPC_IO, + EC2I_SET_SMFI_ENABLE, + EC2I_SET_PMC3_LDN, + EC2I_SET_PMC3_BASE0_MSB, + EC2I_SET_PMC3_BASE0_LSB, + EC2I_SET_PMC3_BASE1_MSB, + EC2I_SET_PMC3_BASE1_LSB, + EC2I_SET_PMC3_IRQ, + EC2I_SET_PMC3_ENABLE, + EC2I_SET_RTCT_LDN, + EC2I_SET_RTCT_P80LB, + EC2I_SET_RTCT_P80LE, + EC2I_SET_RTCT_P80LC, +#ifdef CONFIG_UART_HOST + EC2I_SET_UART2_LDN, + EC2I_SET_UART2_IO_BASE_MSB, + EC2I_SET_UART2_IO_BASE_LSB, + EC2I_SET_UART2_IRQ, + EC2I_SET_UART2_IRQ_TYPE, + EC2I_SET_UART2_ENABLE, +#endif + /* Number of EC2I settings */ + EC2I_SETTING_COUNT +}; + +#endif /* !__ASSEMBLER__ */ +#endif /* __CROS_EC_BOARD_H */ diff --git a/board/it83xx_evb/build.mk b/board/it83xx_evb/build.mk new file mode 100644 index 0000000000..83f36b09b1 --- /dev/null +++ b/board/it83xx_evb/build.mk @@ -0,0 +1,11 @@ +# -*- makefile -*- +# Copyright (c) 2013 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. +# +# Board specific files build + +# the IC is ITE 8380 +CHIP:=it83xx + +board-y=board.o diff --git a/board/it83xx_evb/ec.tasklist b/board/it83xx_evb/ec.tasklist new file mode 100644 index 0000000000..6db02cfa8a --- /dev/null +++ b/board/it83xx_evb/ec.tasklist @@ -0,0 +1,24 @@ +/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/** + * List of enabled tasks in the priority order + * + * The first one has the lowest priority. + * + * For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and + * TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries, + * where : + * 'n' in the name of the task + * 'r' in the main routine of the task + * 'd' in an opaque parameter passed to the routine at startup + * 's' is the stack size in bytes; must be a multiple of 8 + */ +#define CONFIG_TASK_LIST \ + TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \ + TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \ + TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) diff --git a/board/it83xx_evb/gpio.inc b/board/it83xx_evb/gpio.inc new file mode 100644 index 0000000000..51c9167b92 --- /dev/null +++ b/board/it83xx_evb/gpio.inc @@ -0,0 +1,78 @@ +/* -*- mode:c -*- + * + * Copyright (c) 2014 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Declare symbolic names for all the GPIOs that we care about. + * Note: Those with interrupt handlers must be declared first. */ + +GPIO_INT(POWER_BUTTON_L, PIN(E, 4), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt) +GPIO_INT(PCH_PLTRST_L, PIN(E, 3), GPIO_INT_BOTH | GPIO_PULL_UP, lpcrst_interrupt) +GPIO_INT(LID_OPEN, PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_DOWN, lid_interrupt) +GPIO_INT(WP_L, PIN(E, 1), GPIO_INT_BOTH, switch_interrupt) /* Write protect input */ +#ifdef CONFIG_LOW_POWER_IDLE +GPIO_INT(UART1_RX, PIN(B, 0), GPIO_INT_FALLING, uart_deepsleep_interrupt) /* UART1 RX input */ +#endif + +GPIO(CAPS_LED, PIN(H, 1), GPIO_OUT_LOW) +GPIO(SCRO_LED, PIN(H, 2), GPIO_OUT_LOW) +GPIO(PCH_SMI_L, PIN(D, 3), GPIO_OUT_HIGH) +GPIO(PCH_SCI_L, PIN(D, 4), GPIO_OUT_HIGH) +GPIO(GATE_A20_H, PIN(B, 5), GPIO_OUT_HIGH) +GPIO(PCH_RCIN_L, PIN(B, 6), GPIO_OUT_HIGH) +GPIO(LPC_CLKRUN_L, PIN(H, 0), GPIO_OUT_LOW) +GPIO(PCH_WAKE_L, PIN(B, 7), GPIO_ODR_HIGH) /* Wake signal from EC to PCH */ + +GPIO(I2C_A_SCL, PIN(B, 3), GPIO_INPUT) +GPIO(I2C_A_SDA, PIN(B, 4), GPIO_INPUT) +GPIO(I2C_B_SCL, PIN(C, 1), GPIO_INPUT) +GPIO(I2C_B_SDA, PIN(C, 2), GPIO_INPUT) +#ifdef CONFIG_IT83XX_SMCLK2_ON_GPC7 +GPIO(I2C_C_SCL, PIN(C, 7), GPIO_INPUT) +#else +GPIO(I2C_C_SCL, PIN(F, 6), GPIO_INPUT) +#endif +GPIO(I2C_C_SDA, PIN(F, 7), GPIO_INPUT) + +GPIO(I2C_E_SCL, PIN(E, 0), GPIO_INPUT) +GPIO(I2C_E_SDA, PIN(E, 7), GPIO_INPUT) + +#ifdef CONFIG_UART_HOST +GPIO(UART2_SIN1, PIN(H, 1), GPIO_INPUT) +GPIO(UART2_SOUT1, PIN(H, 2), GPIO_INPUT) +#else +GPIO(I2C_D_SCL, PIN(H, 1), GPIO_INPUT) +GPIO(I2C_D_SDA, PIN(H, 2), GPIO_INPUT) +#endif + +/* KSO/KSI pins can be used as GPIO input. */ +GPIO(BOARD_VERSION1, PIN(KSO_H, 5), GPIO_INPUT) +GPIO(BOARD_VERSION2, PIN(KSO_H, 6), GPIO_INPUT) +GPIO(BOARD_VERSION3, PIN(KSO_H, 7), GPIO_INPUT) + +/* Unimplemented signals which we need to emulate for now */ +UNIMPLEMENTED(ENTERING_RW) + +ALTERNATE(PIN_MASK(B, 0x03), 1, MODULE_UART, GPIO_PULL_UP) /* UART1 */ +#ifdef CONFIG_UART_HOST +ALTERNATE(PIN_MASK(H, 0x06), 1, MODULE_UART, 0) /* UART2 */ +#else +ALTERNATE(PIN_MASK(H, 0x06), 1, MODULE_I2C, 0) /* I2C D SCL/SDA H1/H2 */ +#endif +ALTERNATE(PIN_MASK(A, 0x40), 3, MODULE_SPI, 0) /* SSCK of SPI */ +ALTERNATE(PIN_MASK(C, 0x28), 3, MODULE_SPI, 0) /* SMOSI/SMISO of SPI */ +ALTERNATE(PIN_MASK(G, 0x01), 3, MODULE_SPI, 0) /* SSCE1# of SPI */ +ALTERNATE(PIN_MASK(G, 0x04), 3, MODULE_SPI, 0) /* SSCE0# of SPI */ +ALTERNATE(PIN_MASK(A, 0x80), 1, MODULE_PWM, 0) /* PWM7 for FAN1 */ +ALTERNATE(PIN_MASK(D, 0x40), 3, MODULE_PWM, 0) /* TACH0A for FAN1 */ +ALTERNATE(PIN_MASK(B, 0x18), 1, MODULE_I2C, 0) /* I2C A SCL/SDA */ +#ifdef CONFIG_IT83XX_SMCLK2_ON_GPC7 +ALTERNATE(PIN_MASK(C, 0x86), 1, MODULE_I2C, 0) /* I2C B SCL/SDA, C SCL */ +ALTERNATE(PIN_MASK(F, 0x80), 1, MODULE_I2C, 0) /* I2C C SDA */ +#else +ALTERNATE(PIN_MASK(C, 0x06), 1, MODULE_I2C, 0) /* I2C B SCL/SDA */ +ALTERNATE(PIN_MASK(F, 0xC0), 1, MODULE_I2C, 0) /* I2C C SCL/SDA */ +#endif +ALTERNATE(PIN_MASK(E, 0x81), 1, MODULE_I2C, 0) /* I2C E SCL/SDA E0/E7 */ |