baseboard/ite_evb: create ite_evb baseboard

The development board of it83xx and it8xxx2 have common code
and config options which are moved to baseboard ite_evb.

And we create another board for PD EVB based on baseboard ite_evb.

BUG=none
BRANCH=none
TEST=on baseboard ite_evb:
1.test board it83xx_evb and it8xxx2_evb:
successfully Flash EC image and boot on chip it8320 and
it83202.

2.flashrom by ite_spi test:
$ sudo ./util/flash_ec --board=it8xxx2_evb --verbose
INFO: Using servo_v2.
INFO: Using ec image : /mnt/host/source/src/platform/ec/build/
it8xxx2_evb/ec.bin
dut-control --port=9999 i2c_mux_en:on
dut-control --port=9999 i2c_mux:remote_adc
INFO: Flashing chip ite_spi.
dut-control --port=9999 cold_reset:on
dut-control --port=9999 fw_up:on
dut-control --port=9999 cold_reset:off
dut-control --port=9999 fw_up:off
dut-control --port=9999 spi1_vref:pp1800 spi1_buf_en:on
dut-control --port=9999 spi1_buf_on_flex_en:on
INFO: Running flashrom:
 sudo /usr/sbin/flashrom -p ft2232_spi:type=servo-v2,port=B,
serial=911416-00012 --flash-size
flashrom v0.9.9  :  :  on Linux 4.15.0-76-generic (x86_64)
flashrom v0.9.9  :  :  on Linux 4.15.0-76-generic (x86_64)
INFO: Programming EC firmware image.
INFO: Running flashrom:
 /usr/sbin/flashrom -p ft2232_spi:type=servo-v2,port=B,
serial=911416-00012  -w /tmp/flash_spi_6163
flashrom v0.9.9  :  :  on Linux 4.15.0-76-generic (x86_64)
flashrom v0.9.9  :  :  on Linux 4.15.0-76-generic (x86_64)
Calibrating delay loop... OK.
Erasing and writing flash chip... Verifying flash... VERIFIED.
SUCCESS
INFO: Flashing done.
INFO: Restoring servo settings...
dut-control --port=9999 cold_reset:off
dut-control --port=9999 i2c_mux_en:on
dut-control --port=9999 i2c_mux:remote_adc
dut-control --port=9999 spi1_vref:off
dut-control --port=9999 spi1_buf_en:off
dut-control --port=9999 spi1_buf_on_flex_en:off
dut-control --port=9999 cold_reset:on
dut-control --port=9999 cold_reset:off

3.test board it8xxx2_pdevb:
successfully Flash EC image and boot on chip it83202.

Connection with adapter and dongle are able to ready state.

Change-Id: Ib6371b61c27980eb9977548177efb8c896e72d47
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2071551
Reviewed-by: Jett Rink <jettrink@chromium.org>

5 files changed, 218 insertions, 0 deletions

diff --git a/board/it8xxx2_evb/board.c b/board/it8xxx2_evb/board.c
new file mode 100644
index 0000000000..082b8c0d9f
--- /dev/null
+++ b/board/it8xxx2_evb/board.c
@@ -0,0 +1,79 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* IT8xxx2 development board configuration */
+
+#include "adc_chip.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+
+/*
+ * PWM channels. Must be in the exactly same order as in enum pwm_channel.
+ * There total three 16 bits clock prescaler registers for all pwm channels,
+ * so use the same frequency and prescaler register setting is required if
+ * number of pwm channel greater than three.
+ */
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_FAN] = {
+		.channel = PWM_HW_CH_DCR7,
+		.flags = 0,
+		.freq_hz = 30000,
+		.pcfsr_sel = PWM_PRESCALER_C4,
+	},
+	[PWM_CH_WITH_DSLEEP_FLAG] = {
+		.channel = PWM_HW_CH_DCR0,
+		.flags = PWM_CONFIG_DSLEEP,
+		.freq_hz = 100,
+		.pcfsr_sel = PWM_PRESCALER_C6,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
+const struct adc_t adc_channels[] = {
+	/* Convert to mV (3000mV/1024). */
+	[ADC_VBUSSA] = {
+		.name = "ADC_VBUSSA",
+		.factor_mul = ADC_MAX_MVOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+		.channel = CHIP_ADC_CH0, /* GPI0, ADC0 */
+	},
+	[ADC_VBUSSB] = {
+		.name = "ADC_VBUSSB",
+		.factor_mul = ADC_MAX_MVOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+		.channel = CHIP_ADC_CH1, /* GPI1, ADC1 */
+	},
+	[ADC_EVB_CH_13] = {
+		.name = "ADC_EVB_CH_13",
+		.factor_mul = ADC_MAX_MVOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+		.channel = CHIP_ADC_CH13, /* GPL0, ADC13 */
+	},
+	[ADC_EVB_CH_14] = {
+		.name = "ADC_EVB_CH_14",
+		.factor_mul = ADC_MAX_MVOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+		.channel = CHIP_ADC_CH14, /* GPL1, ADC14 */
+	},
+	[ADC_EVB_CH_15] = {
+		.name = "ADC_EVB_CH_15",
+		.factor_mul = ADC_MAX_MVOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+		.channel = CHIP_ADC_CH15, /* GPL2, ADC15 */
+	},
+	[ADC_EVB_CH_16] = {
+		.name = "ADC_EVB_CH_16",
+		.factor_mul = ADC_MAX_MVOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+		.channel = CHIP_ADC_CH16, /* GPL3, ADC16 */
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
diff --git a/board/it8xxx2_evb/board.h b/board/it8xxx2_evb/board.h
new file mode 100644
index 0000000000..1369e43496
--- /dev/null
+++ b/board/it8xxx2_evb/board.h
@@ -0,0 +1,38 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* IT8xxx2 development board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* Select Baseboard features */
+#include "baseboard.h"
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum pwm_channel {
+	PWM_CH_FAN,
+	PWM_CH_WITH_DSLEEP_FLAG,
+	/* Number of PWM channels */
+	PWM_CH_COUNT
+};
+
+enum adc_channel {
+	ADC_VBUSSA,
+	ADC_VBUSSB,
+	ADC_EVB_CH_13,
+	ADC_EVB_CH_14,
+	ADC_EVB_CH_15,
+	ADC_EVB_CH_16,
+	/* Number of ADC channels */
+	ADC_CH_COUNT
+};
+
+#endif /* !__ASSEMBLER__ */
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/it8xxx2_evb/build.mk b/board/it8xxx2_evb/build.mk
new file mode 100644
index 0000000000..2e5c1df6e0
--- /dev/null
+++ b/board/it8xxx2_evb/build.mk
@@ -0,0 +1,14 @@
+# -*- makefile -*-
+# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+
+# the IC is ITE IT8xxx2
+CHIP:=it83xx
+CHIP_FAMILY:=it8xxx2
+CHIP_VARIANT:=it83202bx
+BASEBOARD:=ite_evb
+
+board-y=board.o
diff --git a/board/it8xxx2_evb/ec.tasklist b/board/it8xxx2_evb/ec.tasklist
new file mode 100644
index 0000000000..ff184489e3
--- /dev/null
+++ b/board/it8xxx2_evb/ec.tasklist
@@ -0,0 +1,14 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE)
diff --git a/board/it8xxx2_evb/gpio.inc b/board/it8xxx2_evb/gpio.inc
new file mode 100644
index 0000000000..dd4b88e416
--- /dev/null
+++ b/board/it8xxx2_evb/gpio.inc
@@ -0,0 +1,73 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+GPIO_INT(POWER_BUTTON_L, PIN(E, 4), GPIO_INT_BOTH | GPIO_PULL_UP,   power_button_interrupt)
+#ifndef CONFIG_HOSTCMD_ESPI
+GPIO_INT(PCH_PLTRST_L,   PIN(E, 3), GPIO_INT_BOTH | GPIO_PULL_UP,   lpcrst_interrupt)
+#endif
+GPIO_INT(LID_OPEN,       PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP,   lid_interrupt)
+GPIO_INT(WP_L,           PIN(I, 4), GPIO_INT_BOTH | GPIO_PULL_UP,   switch_interrupt)         /* Write protect input */
+#ifdef CONFIG_LOW_POWER_IDLE
+GPIO_INT(UART1_RX,       PIN(B, 0), GPIO_INT_FALLING | GPIO_PULL_UP, uart_deepsleep_interrupt) /* UART1 RX input */
+#endif
+
+GPIO(PCH_SMI_L,      PIN(D, 3), GPIO_OUT_HIGH)
+GPIO(PCH_SCI_L,      PIN(D, 4), GPIO_OUT_HIGH)
+GPIO(GATE_A20_H,     PIN(B, 5), GPIO_OUT_HIGH)
+GPIO(SYS_RESET_L,    PIN(B, 6), GPIO_OUT_HIGH)
+GPIO(LPC_CLKRUN_L,   PIN(H, 0), GPIO_OUT_LOW)
+GPIO(PCH_WAKE_L,     PIN(B, 7), GPIO_ODR_HIGH) /* Wake signal from EC to PCH */
+
+GPIO(I2C_A_SCL,      PIN(B, 3), GPIO_INPUT)
+GPIO(I2C_A_SDA,      PIN(B, 4), GPIO_INPUT)
+GPIO(I2C_B_SCL,      PIN(C, 1), GPIO_INPUT)
+GPIO(I2C_B_SDA,      PIN(C, 2), GPIO_INPUT)
+#ifdef CONFIG_IT83XX_SMCLK2_ON_GPC7
+GPIO(I2C_C_SCL,      PIN(C, 7), GPIO_INPUT)
+#else
+GPIO(I2C_C_SCL,      PIN(F, 6), GPIO_INPUT)
+#endif
+GPIO(I2C_C_SDA,      PIN(F, 7), GPIO_INPUT)
+
+GPIO(I2C_E_SCL,      PIN(E, 0), GPIO_INPUT)
+GPIO(I2C_E_SDA,      PIN(E, 7), GPIO_INPUT)
+
+#ifdef CONFIG_UART_HOST
+GPIO(UART2_SIN1,     PIN(H, 1), GPIO_INPUT)
+GPIO(UART2_SOUT1,    PIN(H, 2), GPIO_INPUT)
+#endif
+
+/* KSO/KSI pins can be used as GPIO input. */
+GPIO(BOARD_VERSION1, PIN(KSO_H, 5), GPIO_INPUT)
+GPIO(BOARD_VERSION2, PIN(KSO_H, 6), GPIO_INPUT)
+GPIO(BOARD_VERSION3, PIN(KSO_H, 7), GPIO_INPUT)
+
+/* Unimplemented signals which we need to emulate for now */
+UNIMPLEMENTED(ENTERING_RW)
+
+ALTERNATE(PIN_MASK(B, 0x03), 1, MODULE_UART, GPIO_PULL_UP) /* UART1 */
+#ifdef CONFIG_UART_HOST
+ALTERNATE(PIN_MASK(H, 0x06), 1, MODULE_UART, 0)            /* UART2 */
+#endif
+ALTERNATE(PIN_MASK(A, 0x40), 3, MODULE_SPI_MASTER, 0)      /* SSCK of SPI */
+ALTERNATE(PIN_MASK(C, 0x28), 3, MODULE_SPI_MASTER, 0)      /* SMOSI/SMISO of SPI */
+ALTERNATE(PIN_MASK(G, 0x01), 3, MODULE_SPI_MASTER, 0)      /* SSCE1# of SPI */
+ALTERNATE(PIN_MASK(G, 0x04), 3, MODULE_SPI_MASTER, 0)      /* SSCE0# of SPI */
+ALTERNATE(PIN_MASK(A, 0x80), 1, MODULE_PWM, 0)             /* PWM7 for FAN1 */
+ALTERNATE(PIN_MASK(D, 0x40), 3, MODULE_PWM, 0)             /* TACH0A for FAN1 */
+ALTERNATE(PIN_MASK(B, 0x18), 1, MODULE_I2C, 0)             /* I2C A SCL/SDA */
+#ifdef CONFIG_IT83XX_SMCLK2_ON_GPC7
+ALTERNATE(PIN_MASK(C, 0x86), 1, MODULE_I2C, 0)             /* I2C B SCL/SDA, C SCL */
+ALTERNATE(PIN_MASK(F, 0x80), 1, MODULE_I2C, 0)             /* I2C C SDA */
+#else
+ALTERNATE(PIN_MASK(C, 0x06), 1, MODULE_I2C, 0)             /* I2C B SCL/SDA */
+ALTERNATE(PIN_MASK(F, 0xC0), 1, MODULE_I2C, 0)             /* I2C C SCL/SDA */
+#endif
+ALTERNATE(PIN_MASK(E, 0x81), 1, MODULE_I2C, 0)             /* I2C E SCL/SDA E0/E7 */