baseboard/ite_evb: create ite_evb baseboard

The development board of it83xx and it8xxx2 have common code
and config options which are moved to baseboard ite_evb.

And we create another board for PD EVB based on baseboard ite_evb.

BUG=none
BRANCH=none
TEST=on baseboard ite_evb:
1.test board it83xx_evb and it8xxx2_evb:
successfully Flash EC image and boot on chip it8320 and
it83202.

2.flashrom by ite_spi test:
$ sudo ./util/flash_ec --board=it8xxx2_evb --verbose
INFO: Using servo_v2.
INFO: Using ec image : /mnt/host/source/src/platform/ec/build/
it8xxx2_evb/ec.bin
dut-control --port=9999 i2c_mux_en:on
dut-control --port=9999 i2c_mux:remote_adc
INFO: Flashing chip ite_spi.
dut-control --port=9999 cold_reset:on
dut-control --port=9999 fw_up:on
dut-control --port=9999 cold_reset:off
dut-control --port=9999 fw_up:off
dut-control --port=9999 spi1_vref:pp1800 spi1_buf_en:on
dut-control --port=9999 spi1_buf_on_flex_en:on
INFO: Running flashrom:
 sudo /usr/sbin/flashrom -p ft2232_spi:type=servo-v2,port=B,
serial=911416-00012 --flash-size
flashrom v0.9.9  :  :  on Linux 4.15.0-76-generic (x86_64)
flashrom v0.9.9  :  :  on Linux 4.15.0-76-generic (x86_64)
INFO: Programming EC firmware image.
INFO: Running flashrom:
 /usr/sbin/flashrom -p ft2232_spi:type=servo-v2,port=B,
serial=911416-00012  -w /tmp/flash_spi_6163
flashrom v0.9.9  :  :  on Linux 4.15.0-76-generic (x86_64)
flashrom v0.9.9  :  :  on Linux 4.15.0-76-generic (x86_64)
Calibrating delay loop... OK.
Erasing and writing flash chip... Verifying flash... VERIFIED.
SUCCESS
INFO: Flashing done.
INFO: Restoring servo settings...
dut-control --port=9999 cold_reset:off
dut-control --port=9999 i2c_mux_en:on
dut-control --port=9999 i2c_mux:remote_adc
dut-control --port=9999 spi1_vref:off
dut-control --port=9999 spi1_buf_en:off
dut-control --port=9999 spi1_buf_on_flex_en:off
dut-control --port=9999 cold_reset:on
dut-control --port=9999 cold_reset:off

3.test board it8xxx2_pdevb:
successfully Flash EC image and boot on chip it83202.

Connection with adapter and dongle are able to ready state.

Change-Id: Ib6371b61c27980eb9977548177efb8c896e72d47
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2071551
Reviewed-by: Jett Rink <jettrink@chromium.org>

5 files changed, 370 insertions, 0 deletions

diff --git a/board/it8xxx2_pdevb/board.c b/board/it8xxx2_pdevb/board.c
new file mode 100644
index 0000000000..df242908b7
--- /dev/null
+++ b/board/it8xxx2_pdevb/board.c
@@ -0,0 +1,179 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* IT8xxx2 PD development board configuration */
+
+#include "adc_chip.h"
+#include "console.h"
+#include "it83xx_pd.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "timer.h"
+#include "usb_pd_tcpm.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+
+#define USB_PD_PORT_ITE_0   0
+#define USB_PD_PORT_ITE_1   1
+#define USB_PD_PORT_ITE_2   2
+#define RESISTIVE_DIVIDER   11
+
+int board_get_battery_soc(void)
+{
+	CPRINTS("%s", __func__);
+	return 100;
+}
+
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	[USB_PD_PORT_ITE_0] = {
+		.bus_type = EC_BUS_TYPE_EMBEDDED,
+		/* TCPC is embedded within EC so no i2c config needed */
+		.drv = &it83xx_tcpm_drv,
+		/* Alert is active-low, push-pull */
+		.flags = 0,
+	},
+	[USB_PD_PORT_ITE_1] = {
+		.bus_type = EC_BUS_TYPE_EMBEDDED,
+		/* TCPC is embedded within EC so no i2c config needed */
+		.drv = &it83xx_tcpm_drv,
+		/* Alert is active-low, push-pull */
+		.flags = 0,
+	},
+	[USB_PD_PORT_ITE_2] = {
+		.bus_type = EC_BUS_TYPE_EMBEDDED,
+		/* TCPC is embedded within EC so no i2c config needed */
+		.drv = &it83xx_tcpm_drv,
+		/* Alert is active-low, push-pull */
+		.flags = 0,
+	},
+};
+
+void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
+{
+	int cc1_enabled = 0, cc2_enabled = 0;
+
+	if (cc_pin != USBPD_CC_PIN_1)
+		cc2_enabled = enabled;
+	else
+		cc1_enabled = enabled;
+
+	if (port == USBPD_PORT_A) {
+		gpio_set_level(GPIO_USBPD_PORTA_CC2_VCONN, cc2_enabled);
+		gpio_set_level(GPIO_USBPD_PORTA_CC1_VCONN, cc1_enabled);
+	} else if (port == USBPD_PORT_B) {
+		gpio_set_level(GPIO_USBPD_PORTB_CC2_VCONN, cc2_enabled);
+		gpio_set_level(GPIO_USBPD_PORTB_CC1_VCONN, cc1_enabled);
+	} else if (port == USBPD_PORT_C) {
+		gpio_set_level(GPIO_USBPD_PORTC_CC2_VCONN, cc2_enabled);
+		gpio_set_level(GPIO_USBPD_PORTC_CC1_VCONN, cc1_enabled);
+	}
+
+	CPRINTS("p%d Vconn cc1 %d, cc2 %d (On/Off)", port, cc1_enabled,
+		cc2_enabled);
+}
+
+void board_pd_vbus_ctrl(int port, int enabled)
+{
+	CPRINTS("p%d Vbus %d(En/Dis)", port, enabled);
+
+	if (port == USBPD_PORT_A) {
+		gpio_set_level(GPIO_USBPD_PORTA_VBUS_INPUT, !enabled);
+		gpio_set_level(GPIO_USBPD_PORTA_VBUS_OUTPUT, enabled);
+		if (!enabled) {
+			gpio_set_level(GPIO_USBPD_PORTA_VBUS_DROP, 1);
+			udelay(10*MSEC); /* 10ms is a try and error value */
+		}
+		gpio_set_level(GPIO_USBPD_PORTA_VBUS_DROP, 0);
+	} else if (port == USBPD_PORT_B) {
+		gpio_set_level(GPIO_USBPD_PORTB_VBUS_INPUT, !enabled);
+		gpio_set_level(GPIO_USBPD_PORTB_VBUS_OUTPUT, enabled);
+		if (!enabled) {
+			gpio_set_level(GPIO_USBPD_PORTB_VBUS_DROP, 1);
+			udelay(10*MSEC); /* 10ms is a try and error value */
+		}
+		gpio_set_level(GPIO_USBPD_PORTB_VBUS_DROP, 0);
+	} else if (port == USBPD_PORT_C) {
+		gpio_set_level(GPIO_USBPD_PORTC_VBUS_INPUT, !enabled);
+		gpio_set_level(GPIO_USBPD_PORTC_VBUS_OUTPUT, enabled);
+		if (!enabled) {
+			gpio_set_level(GPIO_USBPD_PORTC_VBUS_DROP, 1);
+			udelay(10*MSEC); /* 10ms is a try and error value */
+		}
+		gpio_set_level(GPIO_USBPD_PORTC_VBUS_DROP, 0);
+	}
+
+	if (enabled)
+		udelay(10*MSEC); /* 10ms is a try and error value */
+}
+
+void pd_set_input_current_limit(int port, uint32_t max_ma,
+				uint32_t supply_voltage)
+{
+	CPRINTS("p%d %s", port, __func__);
+}
+
+/*
+ * PWM channels. Must be in the exactly same order as in enum pwm_channel.
+ * There total three 16 bits clock prescaler registers for all pwm channels,
+ * so use the same frequency and prescaler register setting is required if
+ * number of pwm channel greater than three.
+ */
+const struct pwm_t pwm_channels[] = {
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
+const struct adc_t adc_channels[] = {
+	/*
+	 * The register value of ADC reading convert to mV (= register value *
+	 * reading max mV / 10 bit solution 1024).
+	 * NOTE: If the ADC channel measure VBUS:
+	 *       the max reading mv value is the result of resistive divider,
+	 *       so VBUS = reading max mv * resistive divider
+	 *       (check HW schematic).
+	 */
+	[ADC_VBUSSA] = {
+		.name = "ADC_VBUSSA",
+		.factor_mul = ADC_MAX_MVOLT * RESISTIVE_DIVIDER,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+		.channel = CHIP_ADC_CH7, /* GPI7, ADC7 */
+	},
+	[ADC_VBUSSB] = {
+		.name = "ADC_VBUSSB",
+		.factor_mul = ADC_MAX_MVOLT * RESISTIVE_DIVIDER,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+		.channel = CHIP_ADC_CH3, /* GPI3, ADC3 */
+	},
+	[ADC_VBUSSC] = {
+		.name = "ADC_VBUSSC",
+		.factor_mul = ADC_MAX_MVOLT * RESISTIVE_DIVIDER,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+		.channel = CHIP_ADC_CH16, /* GPL0, ADC16 */
+	},
+	[ADC_EVB_CH_13] = {
+		.name = "ADC_EVB_CH_13",
+		.factor_mul = ADC_MAX_MVOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+		.channel = CHIP_ADC_CH13, /* GPL1, ADC13 */
+	},
+	[ADC_EVB_CH_14] = {
+		.name = "ADC_EVB_CH_14",
+		.factor_mul = ADC_MAX_MVOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+		.channel = CHIP_ADC_CH14, /* GPL2, ADC14 */
+	},
+	[ADC_EVB_CH_15] = {
+		.name = "ADC_EVB_CH_15",
+		.factor_mul = ADC_MAX_MVOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+		.channel = CHIP_ADC_CH15, /* GPL3, ADC15 */
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
diff --git a/board/it8xxx2_pdevb/board.h b/board/it8xxx2_pdevb/board.h
new file mode 100644
index 0000000000..3131151980
--- /dev/null
+++ b/board/it8xxx2_pdevb/board.h
@@ -0,0 +1,91 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* IT8xxx2 PD development board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* Select Baseboard features */
+#include "baseboard.h"
+
+/* EC configurations, unnecessarily for PD */
+#undef CONFIG_FANS
+#undef CONFIG_IT83XX_ENABLE_MOUSE_DEVICE
+#undef CONFIG_IT83XX_SMCLK2_ON_GPC7
+#undef CONFIG_KEYBOARD_BOARD_CONFIG
+#undef CONFIG_KEYBOARD_PROTOCOL_8042
+#undef CONFIG_PECI
+#undef CONFIG_PECI_COMMON
+#undef CONFIG_PECI_TJMAX
+#undef CONFIG_POWER_BUTTON
+#undef CONFIG_PWM
+#undef CONFIG_SPI_MASTER
+#undef CONFIG_SPI_FLASH_PORT
+#undef CONFIG_UART_HOST
+#undef CONFIG_HOSTCMD_LPC
+#undef CONFIG_CMD_MMAPINFO
+#undef CONFIG_SWITCH
+
+/* PD */
+#define CONFIG_USB_PD_ALT_MODE
+#define CONFIG_USB_PD_ALT_MODE_DFP
+#define CONFIG_USB_PD_CHECK_MAX_REQUEST_ALLOWED
+#define CONFIG_USB_PD_CUSTOM_PDO
+#define CONFIG_USB_PD_DUAL_ROLE
+#define CONFIG_USB_PD_PORT_MAX_COUNT    3
+#define CONFIG_USB_PD_TCPMV1
+#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP
+#define CONFIG_USB_PD_TRY_SRC
+#define CONFIG_USB_PD_VBUS_DETECT_GPIO
+#define CONFIG_USB_POWER_DELIVERY
+#define CONFIG_USBC_VCONN
+#define CONFIG_USBC_VCONN_SWAP
+#define CONFIG_USB_PD_TCPM_TCPCI
+#define CONFIG_USB_PD_DECODE_SOP
+#define CONFIG_VBOOT_HASH
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum pwm_channel {
+	/* Number of PWM channels */
+	PWM_CH_COUNT
+};
+
+enum adc_channel {
+	ADC_VBUSSA,
+	ADC_VBUSSB,
+	ADC_VBUSSC,
+	ADC_EVB_CH_13,
+	ADC_EVB_CH_14,
+	ADC_EVB_CH_15,
+	/* Number of ADC channels */
+	ADC_CH_COUNT
+};
+
+/* Define typical operating power and max power */
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW       60000
+#define PD_MAX_CURRENT_MA     3000
+/* Try to negotiate to 20V since i2c noise problems should be fixed. */
+#define PD_MAX_VOLTAGE_MV     20000
+/* TODO: determine the following board specific type-C power constants */
+/*
+ * delay to turn on the power supply max is ~16ms.
+ * delay to turn off the power supply max is about ~180ms.
+ */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
+
+/* delay to turn on/off vconn */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
+
+void board_pd_vbus_ctrl(int port, int enabled);
+
+#endif /* !__ASSEMBLER__ */
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/it8xxx2_pdevb/build.mk b/board/it8xxx2_pdevb/build.mk
new file mode 100644
index 0000000000..2e5c1df6e0
--- /dev/null
+++ b/board/it8xxx2_pdevb/build.mk
@@ -0,0 +1,14 @@
+# -*- makefile -*-
+# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+
+# the IC is ITE IT8xxx2
+CHIP:=it83xx
+CHIP_FAMILY:=it8xxx2
+CHIP_VARIANT:=it83202bx
+BASEBOARD:=ite_evb
+
+board-y=board.o
diff --git a/board/it8xxx2_pdevb/ec.tasklist b/board/it8xxx2_pdevb/ec.tasklist
new file mode 100644
index 0000000000..b87c2ca824
--- /dev/null
+++ b/board/it8xxx2_pdevb/ec.tasklist
@@ -0,0 +1,14 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C2, pd_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/it8xxx2_pdevb/gpio.inc b/board/it8xxx2_pdevb/gpio.inc
new file mode 100644
index 0000000000..43b645629d
--- /dev/null
+++ b/board/it8xxx2_pdevb/gpio.inc
@@ -0,0 +1,72 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+GPIO_INT(WP_L,           PIN(I, 4), GPIO_INT_BOTH | GPIO_PULL_UP,   switch_interrupt)          /* Write protect input */
+#ifdef CONFIG_LOW_POWER_IDLE
+GPIO_INT(UART1_RX,       PIN(B, 0), GPIO_INT_FALLING | GPIO_PULL_UP, uart_deepsleep_interrupt) /* UART1 RX input */
+#endif
+
+/*
+ * Because HW port0 and port1 cc pin order invert, FW invert it again.
+ * ex. FW portA pins are mapping to: HW port1 GPF4, GPF5, ADC7, Vbus, Vconn.
+ *     FW portB pins are mapping to: HW port0 GPH1, GPH2, ADC3, Vbus, Vconn.
+ *     FW portC pins are mapping to: HW port3 GPP0, GPP1, ADC16, Vbus, Vconn.
+ */
+GPIO(USBPD_PORTA_VBUS_SEN1P1, PIN(J, 0), GPIO_OUT_LOW)  /* VBUSSEN1P1 */
+GPIO(USBPD_PORTA_VBUS_DROP,   PIN(F, 3), GPIO_OUT_LOW)  /* VBUSDISP1 */
+GPIO(USBPD_PORTA_VBUS_OUTPUT, PIN(F, 1), GPIO_OUT_LOW)  /* VBUSOUTSWENP1 */
+GPIO(USBPD_PORTA_VBUS_INPUT,  PIN(E, 3), GPIO_OUT_HIGH) /* VBUSINSWENP1 */
+GPIO(USBPD_PORTA_VBUS_OV_OC,  PIN(C, 3), GPIO_INPUT)    /* VSWFLTP1 1? */
+GPIO(USBPD_PORTA_CC1_VCONN,   PIN(E, 1), GPIO_OUT_LOW)
+GPIO(USBPD_PORTA_CC2_VCONN,   PIN(J, 5), GPIO_OUT_LOW)
+GPIO(USBPD_PORTA_VCONN_OV_OC, PIN(B, 5), GPIO_INPUT)    /* VCONSWFLTP1 1? */
+GPIO(USBPD_PORTB_VBUS_SEN1P0, PIN(H, 0), GPIO_OUT_LOW)  /* VBUSSEN1P0 */
+GPIO(USBPD_PORTB_VBUS_DROP,   PIN(D, 5), GPIO_OUT_LOW)  /* VBUSDISP0 */
+GPIO(USBPD_PORTB_VBUS_OUTPUT, PIN(A, 6), GPIO_OUT_LOW)  /* VBUSOUTSWENP0 */
+GPIO(USBPD_PORTB_VBUS_INPUT,  PIN(A, 7), GPIO_OUT_HIGH) /* VBUSINSWENP0 */
+GPIO(USBPD_PORTB_VBUS_OV_OC,  PIN(D, 2), GPIO_INPUT)    /* VSWFLTP0 */
+GPIO(USBPD_PORTB_CC1_VCONN,   PIN(A, 5), GPIO_OUT_LOW)
+GPIO(USBPD_PORTB_CC2_VCONN,   PIN(A, 4), GPIO_OUT_LOW)
+GPIO(USBPD_PORTB_VCONN_OV_OC, PIN(D, 4), GPIO_INPUT)    /* VCONSWFLTP0 */
+GPIO(USBPD_PORTC_VBUS_SEN1P3, PIN(P, 2), GPIO_OUT_LOW)  /* VBUSSEN1P3 */
+GPIO(USBPD_PORTC_VBUS_DROP,   PIN(P, 3), GPIO_OUT_LOW)  /* VBUSDISP3 */
+GPIO(USBPD_PORTC_VBUS_OUTPUT, PIN(P, 4), GPIO_OUT_LOW)  /* VBUSOUTSWENP3 */
+GPIO(USBPD_PORTC_VBUS_INPUT,  PIN(P, 5), GPIO_OUT_HIGH) /* VBUSINSWENP3 */
+GPIO(USBPD_PORTC_VBUS_OV_OC,  PIN(P, 6), GPIO_INPUT)    /* VSWFLTP3 */
+GPIO(USBPD_PORTC_CC1_VCONN,   PIN(O, 0), GPIO_OUT_LOW)
+GPIO(USBPD_PORTC_CC2_VCONN,   PIN(O, 1), GPIO_OUT_LOW)
+GPIO(USBPD_PORTC_VCONN_OV_OC, PIN(O, 2), GPIO_INPUT)    /* VCONSWFLTP3 */
+
+GPIO(I2C_A_SCL,      PIN(B, 3), GPIO_INPUT)
+GPIO(I2C_A_SDA,      PIN(B, 4), GPIO_INPUT)
+GPIO(I2C_B_SCL,      PIN(C, 1), GPIO_INPUT)
+GPIO(I2C_B_SDA,      PIN(C, 2), GPIO_INPUT)
+GPIO(I2C_C_SCL,      PIN(F, 6), GPIO_INPUT)
+GPIO(I2C_C_SDA,      PIN(F, 7), GPIO_INPUT)
+GPIO(I2C_E_SCL,      PIN(E, 0), GPIO_INPUT)
+GPIO(I2C_E_SDA,      PIN(E, 7), GPIO_INPUT)
+
+/* KSO/KSI pins can be used as GPIO input. */
+GPIO(BOARD_VERSION1, PIN(KSO_H, 5), GPIO_INPUT)
+GPIO(BOARD_VERSION2, PIN(KSO_H, 6), GPIO_INPUT)
+GPIO(BOARD_VERSION3, PIN(KSO_H, 7), GPIO_INPUT)
+
+/* Unimplemented signals which we need to emulate for now */
+UNIMPLEMENTED(ENTERING_RW)
+UNIMPLEMENTED(PCH_SCI_L)
+UNIMPLEMENTED(PCH_WAKE_L)
+UNIMPLEMENTED(POWER_BUTTON_L)
+UNIMPLEMENTED(LID_OPEN)
+
+ALTERNATE(PIN_MASK(B, 0x03), 1, MODULE_UART, GPIO_PULL_UP) /* UART1 */
+ALTERNATE(PIN_MASK(B, 0x18), 1, MODULE_I2C, 0)             /* I2C A SCL/SDA */
+ALTERNATE(PIN_MASK(C, 0x06), 1, MODULE_I2C, 0)             /* I2C B SCL/SDA */
+ALTERNATE(PIN_MASK(F, 0xC0), 1, MODULE_I2C, 0)             /* I2C C SCL/SDA */
+ALTERNATE(PIN_MASK(E, 0x81), 1, MODULE_I2C, 0)             /* I2C E SCL/SDA E0/E7 */