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| author | Keith Short <keithshort@chromium.org> | 2020-03-04 12:53:25 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-04-09 00:56:31 +0000 |
| commit | 3b831bbf6ee24a09ef65064d7374e6ef7960eedf (patch) | |
| tree | 1e60e398e159b257a3cba56bc037844d0b289d84 /board/jslrvp_ite/board.c | |
| parent | 4d39614441258dc5788c2a55000abe56ac43d3fe (diff) | |
| download | chrome-ec-3b831bbf6ee24a09ef65064d7374e6ef7960eedf.tar.gz | |
icelake: Cleanup power sequencing for IceLake/TigerLake/JasperLake
Configure PWROK generation related signals for Ice Lake, Tiger Lake, and
Jasper Lake SoCs. The array driven sequencing provides better
flexibility for the PWROK signals, some of which may be automatically
handled by the platform and some require EC control.
BUG=b:150726713
BRANCH=none
TEST=make buildall
TEST=Volteer: verify VCCIN enable and SYS_PWROK generation during S0 and
verify signals are deasserted when exiting S0.
TEST=Wadledoo: verified 2ms delay between ALL_SYS_PWRGD and PCH_PWROK,
verified JPL sequences to S0.
Change-Id: Iceae29c65398643839b31f6cd757352282849fda
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2088285
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Diffstat (limited to 'board/jslrvp_ite/board.c')
| -rw-r--r-- | board/jslrvp_ite/board.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/board/jslrvp_ite/board.c b/board/jslrvp_ite/board.c index bb41fedcc9..5ea6f057b6 100644 --- a/board/jslrvp_ite/board.c +++ b/board/jslrvp_ite/board.c @@ -10,6 +10,7 @@ #include "driver/charger/isl923x.h" #include "extpower.h" #include "i2c.h" +#include "icelake.h" #include "intc.h" #include "lid_switch.h" #include "power.h" @@ -101,6 +102,18 @@ const struct charger_config_t chg_chips[] = { const unsigned int chg_cnt = ARRAY_SIZE(chg_chips); +/******************************************************************************/ +/* PWROK signal configuration */ +/* + * On JSLRVP the ALL_SYS_PWRGD, VCCST_PWRGD, PCH_PWROK, and SYS_PWROK + * signals are handled by the board. No EC control needed. + */ +const struct intel_x86_pwrok_signal pwrok_signal_assert_list[] = {}; +const int pwrok_signal_assert_count = ARRAY_SIZE(pwrok_signal_assert_list); + +const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[] = {}; +const int pwrok_signal_deassert_count = ARRAY_SIZE(pwrok_signal_assert_list); + /* * Returns board information (board id[7:0] and Fab id[15:8]) on success * -1 on error. |