diff options
author | David Huang <david.huang@quanta.corp-partner.google.com> | 2021-08-16 17:58:40 +0800 |
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committer | Commit Bot <commit-bot@chromium.org> | 2021-08-23 04:32:27 +0000 |
commit | b3d803095bb271f506c1eb00e45c66f7d99cb53e (patch) | |
tree | d2936b0351e3f9cacc88d4f77983911f09f51e9a /board/kano/gpio.inc | |
parent | 745b4683e5e9dd9a26340906e68ae15ee775460c (diff) | |
download | chrome-ec-b3d803095bb271f506c1eb00e45c66f7d99cb53e.tar.gz |
kano: remove usb port C2 and board ID 1 related function
Remove usb port C2 and board ID 1 related function.
BUG=b:192370253
BRANCH=brya
TEST=make buildall -j succeeded.
Signed-off-by: David Huang <david.huang@quanta.corp-partner.google.com>
Change-Id: Ie051e44424bdf9e1de6d1b13afddea10ef85ff3e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3098121
Reviewed-by: caveh jalali <caveh@chromium.org>
Diffstat (limited to 'board/kano/gpio.inc')
-rw-r--r-- | board/kano/gpio.inc | 40 |
1 files changed, 1 insertions, 39 deletions
diff --git a/board/kano/gpio.inc b/board/kano/gpio.inc index 79a97b0475..2991583124 100644 --- a/board/kano/gpio.inc +++ b/board/kano/gpio.inc @@ -28,47 +28,9 @@ */ GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW) -/* - * GPIOE1 is an ALT function ADC INPUT on board ID 2 and a GPIO INPUT on - * board ID 1. This declaration gives us a signal name to use on board - * ID 1. - */ -GPIO(ID_1_EC_BATT_PRES_ODL, PIN(E, 1), GPIO_INPUT) - -/* - * GPIO34 is an INPUT on board ID 2 and ODR_LOW on board ID 1. - * - * Since this pin is pulled up to 3.3V through a 30.9K ohm resistor on - * board ID 2, we will leak about 0.3mW until the pin is put in ALT mode - * when MODULE_ADC configuration runs. Initializing the pin to ODR_LOW - * gives us full control on both boards. - */ -GPIO(ID_1_USB_C0_C2_TCPC_RST_ODL, PIN(3, 4), GPIO_ODR_LOW) - -/* Board ID 1 IO expander configuration */ - -IOEX(ID_1_USB_C0_RT_RST_ODL, EXPIN(IOEX_ID_1_C0_NCT38XX, 0, 2), GPIO_ODR_LOW) -/* GPIO03_P1 to PU */ -IOEX(ID_1_USB_C0_FRS_EN, EXPIN(IOEX_ID_1_C0_NCT38XX, 0, 4), GPIO_LOW) -IOEX(ID_1_USB_C0_OC_ODL, EXPIN(IOEX_ID_1_C0_NCT38XX, 0, 6), GPIO_ODR_HIGH) -/* GPIO07_P1 to PU */ - -IOEX(ID_1_USB_C2_RT_RST_ODL, EXPIN(IOEX_ID_1_C2_NCT38XX, 0, 2), GPIO_ODR_LOW) -/* GPIO03_P2 to PU */ -IOEX(ID_1_USB_C2_FRS_EN, EXPIN(IOEX_ID_1_C2_NCT38XX, 0, 4), GPIO_LOW) -IOEX(ID_1_USB_C1_OC_ODL, EXPIN(IOEX_ID_1_C2_NCT38XX, 0, 6), GPIO_ODR_HIGH) -IOEX(ID_1_USB_C2_OC_ODL, EXPIN(IOEX_ID_1_C2_NCT38XX, 0, 7), GPIO_ODR_HIGH) - -/* Board ID 2 IO expander configuration */ -/* GPIO02_P2 to PU */ -/* GPIO03_P2 to PU */ IOEX(USB_C0_OC_ODL, EXPIN(IOEX_C0_NCT38XX, 0, 4), GPIO_ODR_HIGH) IOEX(USB_C0_FRS_EN, EXPIN(IOEX_C0_NCT38XX, 0, 6), GPIO_LOW) IOEX(USB_C0_RT_RST_ODL, EXPIN(IOEX_C0_NCT38XX, 0, 7), GPIO_ODR_LOW) -IOEX(USB_C2_RT_RST_ODL, EXPIN(IOEX_C2_NCT38XX, 0, 2), GPIO_ODR_LOW) -IOEX(USB_C1_OC_ODL, EXPIN(IOEX_C2_NCT38XX, 0, 3), GPIO_ODR_HIGH) -IOEX(USB_C2_OC_ODL, EXPIN(IOEX_C2_NCT38XX, 0, 4), GPIO_ODR_HIGH) -IOEX(USB_C2_FRS_EN, EXPIN(IOEX_C2_NCT38XX, 0, 6), GPIO_LOW) -/* GPIO07_P2 to PU */ +GPIO(USB_C1_OC_ODL, PIN(E, 1), GPIO_ODR_HIGH) |