diff options
author | Vic (Chun-Ju) Yang <victoryang@chromium.org> | 2014-04-28 15:02:16 +0800 |
---|---|---|
committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2014-04-30 09:49:05 +0000 |
commit | a0d6ac7166d96819d6aa90562c295c2f9d943ded (patch) | |
tree | 85a983f06ea595c6466e41e69001ea9f9024e83e /board/keyborg/hardware.c | |
parent | 1b7573c3e9484b35ee62c1160719076e8e9d8837 (diff) | |
download | chrome-ec-a0d6ac7166d96819d6aa90562c295c2f9d943ded.tar.gz |
Keyborg: Refine master slave identification
The current identification method uses SPI_NSS as master/slave
indication. However, if the other chip is not reset at the same time, it
would drive SPI_NSS and fails the identification.
Since the master chip is equipped with USB connection, we can identify
the chips with USB pull up pin, which doesn't suffer from this problem.
Also updates the comments on pin usage.
BUG=None
TEST=Reset the chips repeatedly.
BRANCH=None
Change-Id: Iccd7e73fca85abfa554f90dcb7e354cc4cc04626
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/197194
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'board/keyborg/hardware.c')
-rw-r--r-- | board/keyborg/hardware.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/board/keyborg/hardware.c b/board/keyborg/hardware.c index 6651cf5b46..c8c106f92b 100644 --- a/board/keyborg/hardware.c +++ b/board/keyborg/hardware.c @@ -66,21 +66,23 @@ static void pins_init(void) STM32_GPIO_AFIO_MAPR = (STM32_GPIO_AFIO_MAPR & ~(0x7 << 24)) | (2 << 24); - /* Pin usage: + /* + * Initial pin usage: * PA0: SPI_NSS - INPUT/INT_FALLING - * PA1: N_CHG - OUTPUT/LOW + * PA1: N_CHG - INPUT * PA3: SPI_CLK - INPUT * PA4: SPI_MISO - INPUT * PA6: CS1 - OUTPUT/HIGH * PA7: SPI_MOSI - INPUT + * PA9: USB_PU - OUTPUT/LOW * PA15: UART TX - OUTPUT/HIGH * PI1: SYNC1 - OUTPUT/LOW * PI2: SYNC2 - OUTPUT/LOW */ - STM32_GPIO_CRL(GPIO_A) = FLOAT(0) | OUT(1) | FLOAT(3) | FLOAT(4) | + STM32_GPIO_CRL(GPIO_A) = FLOAT(0) | FLOAT(1) | FLOAT(3) | FLOAT(4) | OUT(6) | FLOAT(7); - STM32_GPIO_CRH(GPIO_A) = OUT(15); - STM32_GPIO_BSRR(GPIO_A) = LOW(1) | HIGH(6) | HIGH(15); + STM32_GPIO_CRH(GPIO_A) = OUT(9) | OUT(15); + STM32_GPIO_BSRR(GPIO_A) = LOW(1) | HIGH(6) | LOW(9) | HIGH(15); STM32_EXTI_FTSR |= INT(0); STM32_GPIO_CRL(GPIO_I) = OUT(1) | OUT(2); |