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| author | Yilun Lin <yllin@google.com> | 2019-03-18 16:36:48 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2019-03-27 05:57:29 -0700 |
| commit | 4a2a450ca48278b9f701461799df54faa6c4c395 (patch) | |
| tree | fa9a65559f4ba47a45d146bbada669c567fea0d5 /board/kukui_scp | |
| parent | 6a144d98d3d09c2beea3ae5002a371a4f71a23f0 (diff) | |
| download | chrome-ec-4a2a450ca48278b9f701461799df54faa6c4c395.tar.gz | |
mt_scp: Support ROM section on internal SRAM.
Currently, kukui_scp's memory layout interleaves with RO and RW
sections. This complicates the MPU region configuration, and it
even unconfigurable.
This CL propose to simplify the layout and configuration by introducing
an IROM region, and re-layout the memory.
New layout would be:
---------------------------- 0x0
RO| .stepping_stone
| .text .rodata .data LMA
---------------------------- 0x100000
RW| .bss .data stack
| ipi shared buffer
---------------------------- 0x7C0000
BRANCH=None
BUG=b:123269246
TEST=1. w/o this CL: make buildall -j; mv build build.old
2. w/ this CL: make buildall -j;
3. compare smap by: ls build/*/*/ec.*.smap | \
sed -e 's|build/||' | \
xargs -I{} diff build/{} build.old/{}
and sees that only kukui_scp's smap changed.
Change-Id: I875a28c6b325ba66afe0387d3ea244190ddccde8
Signed-off-by: Yilun Lin <yllin@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1530263
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Yilun Lin <yllin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'board/kukui_scp')
| -rw-r--r-- | board/kukui_scp/board.h | 23 |
1 files changed, 13 insertions, 10 deletions
diff --git a/board/kukui_scp/board.h b/board/kukui_scp/board.h index 7bd60c306a..85dbd49c66 100644 --- a/board/kukui_scp/board.h +++ b/board/kukui_scp/board.h @@ -20,20 +20,23 @@ * +-------------------- 0x0 * | ptr to stack_top 0x0 * | ptr to reset func 0x04 - * |-------------------- 0x08 - * | free shared space with AP - * +-------------------- 0x005B0 - * | IPI shared buffer with AP (288 + 8) * 2 * +-------------------- 0x00800 - * | scp.img, exception vectors starting location. - * +-------------------- 0x7B800 - * | free shared space with AP 2KB + * | ROM vectortable, .text, .rodata, .data LMA + * +-------------------- 0x10000 + * | RAM .bss, .data + * +-------------------- 0x7BDB0 + * | IPI shared buffer with AP (288 + 8) * 2 * +-------------------- 0x7C000 * | 8KB I-CACHE * +-------------------- 0x7E000 + * | 8KB D-CACHE + * +-------------------- 0x80000 */ -#define CONFIG_RAM_BASE 0x00800 -#define CONFIG_RAM_SIZE 0x7B000 +#define ICACHE_BASE 0x7C000 +#define CONFIG_ROM_BASE 0x00800 +#define CONFIG_RAM_BASE 0x10000 +#define CONFIG_ROM_SIZE (CONFIG_RAM_BASE - CONFIG_ROM_BASE) +#define CONFIG_RAM_SIZE (CONFIG_IPC_SHARED_OBJ_ADDR - CONFIG_RAM_BASE) #define CONFIG_RO_MEM_OFF 0 /* Access DRAM through cached access */ @@ -45,7 +48,7 @@ /* IPI configs */ #define CONFIG_IPC_SHARED_OBJ_BUF_SIZE 288 #define CONFIG_IPC_SHARED_OBJ_ADDR \ - (CONFIG_RAM_BASE - \ + (ICACHE_BASE - \ (CONFIG_IPC_SHARED_OBJ_BUF_SIZE + 2 * 4 /* int32_t */) * 2) #define CONFIG_IPI #define CONFIG_RPMSG_NAME_SERVICE |