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| author | Keith Short <keithshort@chromium.org> | 2021-08-06 14:24:57 -0600 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-11-19 23:28:44 +0000 |
| commit | f2809b72c935beb26e1b29f6fa01fb851cadc492 (patch) | |
| tree | 965d74aba514632e71314db8c4287d67897f05df /board/mchpevb1 | |
| parent | b91e9c7c83f47c392c94f571d699e94dd568797f (diff) | |
| download | chrome-ec-f2809b72c935beb26e1b29f6fa01fb851cadc492.tar.gz | |
config: rename CONFIG_HOSTCMD_ESPI to CONFIG_HOST_INTERFACE_ESPI
Rename CONFIG_HOSTCMD_ESPI to CONFIG_HOST_INTERFACE_ESPI. This makes the
host interface selection configs distinct from configs used to
enable/disable specific host commands.
BUG=b:195416058
BRANCH=main
TEST=compare_build.sh
Signed-off-by: Keith Short <keithshort@chromium.org>
Change-Id: I7f52614ca9a0dd54cc7e96e51bba40453564198e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3095842
Tested-by: Michał Barnaś <mb@semihalf.com>
Diffstat (limited to 'board/mchpevb1')
| -rw-r--r-- | board/mchpevb1/board.h | 2 | ||||
| -rw-r--r-- | board/mchpevb1/gpio.inc | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/board/mchpevb1/board.h b/board/mchpevb1/board.h index de1e7a75e9..e16d0bb10f 100644 --- a/board/mchpevb1/board.h +++ b/board/mchpevb1/board.h @@ -163,7 +163,7 @@ #define CONFIG_CHIPSET_SKYLAKE #define CONFIG_CHIPSET_RESET_HOOK -#define CONFIG_HOSTCMD_ESPI +#define CONFIG_HOST_INTERFACE_ESPI #define CONFIG_HOSTCMD_ESPI_VW_SLP_S3 #define CONFIG_HOSTCMD_ESPI_VW_SLP_S4 #define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD diff --git a/board/mchpevb1/gpio.inc b/board/mchpevb1/gpio.inc index 8be1099fbd..3949e31843 100644 --- a/board/mchpevb1/gpio.inc +++ b/board/mchpevb1/gpio.inc @@ -27,8 +27,8 @@ #define GPIO_BOTH_EDGES_PU (GPIO_INT_BOTH | GPIO_PULL_UP) -/* Only needed if CONFIG_HOSTCMD_ESPI is not set, using LPC interface to PCH */ -#ifndef CONFIG_HOSTCMD_ESPI +/* Only needed if CONFIG_HOST_INTERFACE_ESPI is not set, using LPC interface to PCH */ +#ifndef CONFIG_HOST_INTERFACE_ESPI GPIO_INT(PCH_PLTRST_L, PIN(064), GPIO_BOTH_EDGES_PU, lpcrst_interrupt) #endif |