diff options
| author | Diana Z <dzigterman@chromium.org> | 2018-10-01 15:14:12 -0600 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-10-09 16:26:47 -0700 |
| commit | bb3f5b55257bf9ae1a0c695e4b8f870932137472 (patch) | |
| tree | 700d9cdfa331d6bfd0a11646c88c0b24338592a8 /board/meep/gpio.inc | |
| parent | e79a7346922507aa12ecf6f488921f7d57ca7a95 (diff) | |
| download | chrome-ec-bb3f5b55257bf9ae1a0c695e4b8f870932137472.tar.gz | |
Octopus: add reset logic for C0 TCPC
This change adds a call to the C0 TCPC reset for standalone TCPC boards
which have that pin hooked up in hardware, and adds the GPIO as
unimplemented for boards which do not have this yet.
BRANCH=None
BUG=b:112756630
TEST=Added a log print and rebooted EC on bobba to verify TCPC C0 reset,
then verified that charging on C0 worked. Also imaged yorp proto 2 and
rebooted, verifying C0 reset was not attempted.
Change-Id: I615861f0d9ce9b5a89692e3982ed2e19c7e0b237
Signed-off-by: Diana Z <dzigterman@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1257647
Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'board/meep/gpio.inc')
| -rw-r--r-- | board/meep/gpio.inc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/board/meep/gpio.inc b/board/meep/gpio.inc index b05068d011..6b3d5c8a6f 100644 --- a/board/meep/gpio.inc +++ b/board/meep/gpio.inc @@ -129,6 +129,9 @@ GPIO(USB_C1_BC12_CHG_DET_L, PIN(E, 4), GPIO_INPUT) /* C1 BC1.2 Detect */ GPIO(USB_C1_HPD_1V8_ODL, PIN(C, 6), GPIO_INPUT | /* C1 DP Hotplug Detect */ GPIO_SEL_1P8V) +/* Not implemented in hardware yet */ +UNIMPLEMENTED(USB_C0_PD_RST) + /* * USB2_OTG_ID is 1.8V pin on the SoC side with an internal pull-up. However, it * 3.3V on the EC side. So, configure it as ODR so that the EC never drives it |