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| author | Zick Wei <zick.wei@quanta.corp-partner.google.com> | 2020-06-20 15:11:09 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-06-25 20:32:41 +0000 |
| commit | 797c10f87b7adc4adabc0624c253d9b32d0956c8 (patch) | |
| tree | d56e3ef8d11fc1928bc3fbe925e71a8f306a5153 /board/morphius/board.c | |
| parent | d77a371e0a20a2af5ddb53b13c2588ea9d70eb57 (diff) | |
| download | chrome-ec-797c10f87b7adc4adabc0624c253d9b32d0956c8.tar.gz | |
berknip/morphius: update gpio S0_PWROK_OD
This patch update S0_PWROK_OD for schematic change.
BUG=b:150278507, b:152841287
BRANCH=none
TEST=make buildall, verify EC code can power on rework MB.
Signed-off-by: Zick Wei <zick.wei@quanta.corp-partner.google.com>
Change-Id: Iaf8f2458c2dfe49f40eada8dced1febe2c4c4687
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2255826
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Commit-Queue: Edward Hill <ecgh@chromium.org>
Tested-by: Edward Hill <ecgh@chromium.org>
Diffstat (limited to 'board/morphius/board.c')
| -rw-r--r-- | board/morphius/board.c | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/board/morphius/board.c b/board/morphius/board.c index 869e86e933..ac370086d9 100644 --- a/board/morphius/board.c +++ b/board/morphius/board.c @@ -577,3 +577,46 @@ void ps2_pwr_en_interrupt(enum gpio_signal signal) { hook_call_deferred(&trackpoint_reset_deferred_data, MSEC); } + +/***************************************************************************** + * Power signals + */ + +struct power_signal_info power_signal_list[] = { + [X86_SLP_S3_N] = { + .gpio = GPIO_PCH_SLP_S3_L, + .flags = POWER_SIGNAL_ACTIVE_HIGH, + .name = "SLP_S3_DEASSERTED", + }, + [X86_SLP_S5_N] = { + .gpio = GPIO_PCH_SLP_S5_L, + .flags = POWER_SIGNAL_ACTIVE_HIGH, + .name = "SLP_S5_DEASSERTED", + }, + [X86_S0_PGOOD] = { + .gpio = GPIO_S0_PWROK_OD_V0, + .flags = POWER_SIGNAL_ACTIVE_HIGH, + .name = "S0_PGOOD", + }, + [X86_S5_PGOOD] = { + .gpio = GPIO_S5_PGOOD, + .flags = POWER_SIGNAL_ACTIVE_HIGH, + .name = "S5_PGOOD", + }, +}; +BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); + +enum gpio_signal GPIO_S0_PGOOD = GPIO_S0_PWROK_OD_V0; + +void board_version_check(void) +{ + uint32_t board_ver = 0; + + cbi_get_board_version(&board_ver); + + if (board_ver == 3) { + power_signal_list[X86_S0_PGOOD].gpio = GPIO_S0_PWROK_OD_V1; + GPIO_S0_PGOOD = GPIO_S0_PWROK_OD_V1; + } +} +DECLARE_HOOK(HOOK_INIT, board_version_check, HOOK_PRIO_INIT_I2C); |