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author | Zick Wei <zick.wei@quanta.corp-partner.google.com> | 2020-06-20 15:11:09 +0800 |
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committer | Commit Bot <commit-bot@chromium.org> | 2020-06-25 20:32:41 +0000 |
commit | 797c10f87b7adc4adabc0624c253d9b32d0956c8 (patch) | |
tree | d56e3ef8d11fc1928bc3fbe925e71a8f306a5153 /board/morphius | |
parent | d77a371e0a20a2af5ddb53b13c2588ea9d70eb57 (diff) | |
download | chrome-ec-797c10f87b7adc4adabc0624c253d9b32d0956c8.tar.gz |
berknip/morphius: update gpio S0_PWROK_OD
This patch update S0_PWROK_OD for schematic change.
BUG=b:150278507, b:152841287
BRANCH=none
TEST=make buildall, verify EC code can power on rework MB.
Signed-off-by: Zick Wei <zick.wei@quanta.corp-partner.google.com>
Change-Id: Iaf8f2458c2dfe49f40eada8dced1febe2c4c4687
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2255826
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Commit-Queue: Edward Hill <ecgh@chromium.org>
Tested-by: Edward Hill <ecgh@chromium.org>
Diffstat (limited to 'board/morphius')
-rw-r--r-- | board/morphius/board.c | 43 | ||||
-rw-r--r-- | board/morphius/board.h | 6 | ||||
-rw-r--r-- | board/morphius/gpio.inc | 3 |
3 files changed, 50 insertions, 2 deletions
diff --git a/board/morphius/board.c b/board/morphius/board.c index 869e86e933..ac370086d9 100644 --- a/board/morphius/board.c +++ b/board/morphius/board.c @@ -577,3 +577,46 @@ void ps2_pwr_en_interrupt(enum gpio_signal signal) { hook_call_deferred(&trackpoint_reset_deferred_data, MSEC); } + +/***************************************************************************** + * Power signals + */ + +struct power_signal_info power_signal_list[] = { + [X86_SLP_S3_N] = { + .gpio = GPIO_PCH_SLP_S3_L, + .flags = POWER_SIGNAL_ACTIVE_HIGH, + .name = "SLP_S3_DEASSERTED", + }, + [X86_SLP_S5_N] = { + .gpio = GPIO_PCH_SLP_S5_L, + .flags = POWER_SIGNAL_ACTIVE_HIGH, + .name = "SLP_S5_DEASSERTED", + }, + [X86_S0_PGOOD] = { + .gpio = GPIO_S0_PWROK_OD_V0, + .flags = POWER_SIGNAL_ACTIVE_HIGH, + .name = "S0_PGOOD", + }, + [X86_S5_PGOOD] = { + .gpio = GPIO_S5_PGOOD, + .flags = POWER_SIGNAL_ACTIVE_HIGH, + .name = "S5_PGOOD", + }, +}; +BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); + +enum gpio_signal GPIO_S0_PGOOD = GPIO_S0_PWROK_OD_V0; + +void board_version_check(void) +{ + uint32_t board_ver = 0; + + cbi_get_board_version(&board_ver); + + if (board_ver == 3) { + power_signal_list[X86_S0_PGOOD].gpio = GPIO_S0_PWROK_OD_V1; + GPIO_S0_PGOOD = GPIO_S0_PWROK_OD_V1; + } +} +DECLARE_HOOK(HOOK_INIT, board_version_check, HOOK_PRIO_INIT_I2C); diff --git a/board/morphius/board.h b/board/morphius/board.h index 33c733077a..bb429b0135 100644 --- a/board/morphius/board.h +++ b/board/morphius/board.h @@ -47,6 +47,8 @@ #define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL #define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL +#define CONFIG_POWER_SIGNAL_RUNTIME_CONFIG + /* GPIO mapping from board specific name to EC common name. */ #define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL #define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL @@ -63,7 +65,6 @@ #define GPIO_PCH_SYS_PWROK GPIO_EC_FCH_PWROK #define GPIO_PCH_WAKE_L GPIO_EC_FCH_WAKE_L #define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL -#define GPIO_S0_PGOOD GPIO_S0_PWROK_OD #define GPIO_S5_PGOOD GPIO_EC_PWROK_OD #define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L #define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL @@ -76,6 +77,9 @@ #ifndef __ASSEMBLER__ +/* This GPIOs moved. Temporarily detect and support the V0 HW. */ +extern enum gpio_signal GPIO_S0_PGOOD; + void ps2_pwr_en_interrupt(enum gpio_signal signal); enum adc_channel { diff --git a/board/morphius/gpio.inc b/board/morphius/gpio.inc index 720565f7bb..f3578d5b4a 100644 --- a/board/morphius/gpio.inc +++ b/board/morphius/gpio.inc @@ -16,7 +16,8 @@ GPIO_INT(USB_C0_BC12_INT_ODL, PIN(9, 3), GPIO_INT_FALLING | GPIO_PULL_UP, bc12_i GPIO_INT(USB_C1_BC12_INT_ODL, PIN(A, 4), GPIO_INT_FALLING | GPIO_PULL_UP, bc12_interrupt) GPIO_INT(SLP_S3_L, PIN(7, 4), GPIO_INT_BOTH, power_signal_interrupt) GPIO_INT(SLP_S5_L, PIN(E, 0), GPIO_INT_BOTH, power_signal_interrupt) -GPIO_INT(S0_PWROK_OD, PIN(5, 6), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(S0_PWROK_OD_V0, PIN(5, 6), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(S0_PWROK_OD_V1, PIN(B, 1), GPIO_INT_BOTH, power_signal_interrupt) GPIO_INT(EC_PWROK_OD, PIN(3, 7), GPIO_INT_BOTH, power_signal_interrupt) GPIO_INT(EC_PWR_BTN_ODL, PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt) GPIO_INT(LID_OPEN, PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt) |