diff options
| author | Daisuke Nojiri <dnojiri@chromium.org> | 2019-04-15 17:58:41 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-03-25 07:30:24 +0000 |
| commit | 6131cedc7160d6f71245992fa5e7bf1f7acb70c4 (patch) | |
| tree | 20576edae32e45516235b065e37ed3d051aa4d7d /board/nami/gpio.inc | |
| parent | 44102b64294f2437e06760ef20e143134e02dc22 (diff) | |
| download | chrome-ec-6131cedc7160d6f71245992fa5e7bf1f7acb70c4.tar.gz | |
Nami: Set TCPC_AUX_SWITCH to 0xC on Port 1 on CCD enable
When the screen brightness is changed, DP sends signal on AUX channel.
This causes CCD mode to be disconnected.
This patch sets the MUX to aux+ <-> sbu2, aux- <-> sbu1 to fix it.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=b/113266817
BRANCH=nami
TEST=Verify on Syndra UART over CCD doesn't get disconnected when the
screen brightness is changed.
Change-Id: I3dba1bdfd44a921077a2f60dec17119bb0077238
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1595212
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Auto-Submit: Daisuke Nojiri <dnojiri@chromium.org>
Diffstat (limited to 'board/nami/gpio.inc')
| -rw-r--r-- | board/nami/gpio.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/nami/gpio.inc b/board/nami/gpio.inc index 7bc922edaa..f4119c96a6 100644 --- a/board/nami/gpio.inc +++ b/board/nami/gpio.inc @@ -35,6 +35,7 @@ GPIO_INT(USB_C0_BC12_INT_L, PIN(D, 2), GPIO_INT_FALLING, usb0_evt) GPIO_INT(USB_C1_BC12_INT_L, PIN(D, 3), GPIO_INT_FALLING, usb1_evt) GPIO_INT(ACCELGYRO3_INT_L, PIN(3, 6), GPIO_INT_FALLING | GPIO_PULL_UP, bmi160_interrupt) GPIO_INT(TABLET_MODE_L, PIN(7, 2), GPIO_INT_BOTH, gmr_tablet_switch_isr) +GPIO_INT(CCD_MODE_ODL, PIN(6, 3), GPIO_INT_FALLING, ccd_mode_isr) GPIO(ENABLE_BACKLIGHT_L, PIN(6, 7), GPIO_OUT_LOW) /* LCD backlight */ GPIO(PP3300_DX_WLAN, PIN(B, 1), GPIO_OUT_LOW) /* Enable WLAN 3.3V Power */ @@ -47,7 +48,6 @@ GPIO(EC_PLATFORM_RST, PIN(4, 5), GPIO_OUT_LOW) /* EC Reset to LDO_EN */ GPIO(SYS_RESET_L, PIN(6, 1), GPIO_ODR_HIGH) /* Cold Reset to SOC */ GPIO(PMIC_SLP_SUS_L, PIN(8, 5), GPIO_OUT_LOW) /* SLP_SUS# to PMIC */ GPIO(BATTERY_PRESENT_L, PIN(3, 4), GPIO_INPUT) /* Battery Present */ -GPIO(CCD_MODE_ODL, PIN(6, 3), GPIO_INPUT) /* Case Closed Debug Mode */ GPIO(ENTERING_RW, PIN(7, 6), GPIO_OUTPUT) /* EC Entering RW */ GPIO(PMIC_INT_L, PIN(6, 0), GPIO_INPUT) /* PMIC interrupt */ #ifndef CONFIG_POWER_S0IX |