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authorDaisuke Nojiri <dnojiri@chromium.org>2018-07-18 12:10:52 -0700
committerchrome-bot <chrome-bot@chromium.org>2018-07-24 12:44:19 -0700
commit7820a3e2208effbbc1d49580e2dc8dc02a71cc97 (patch)
treec7f9105b9b3bdf89b138262d14b809034bc8adc7 /board/nami
parentf90ba97009758fae93add43894d722886a0ba007 (diff)
downloadchrome-ec-7820a3e2208effbbc1d49580e2dc8dc02a71cc97.tar.gz
Nami: Reverse polarity of USB2_ID
USB2_ID controlls OTG functionality on the SoC. The polarity is currently reversed. This patch fixes it. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:110385436 BRANCH=none TEST=Verify USB2 host devices work through USB-C port. Change-Id: I8cf67395dacf75828b80226eb1975de647ff5376 Reviewed-on: https://chromium-review.googlesource.com/1142386 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Diffstat (limited to 'board/nami')
-rw-r--r--board/nami/gpio.inc2
-rw-r--r--board/nami/usb_pd_policy.c3
2 files changed, 2 insertions, 3 deletions
diff --git a/board/nami/gpio.inc b/board/nami/gpio.inc
index 0a4708dda8..546e5aaf56 100644
--- a/board/nami/gpio.inc
+++ b/board/nami/gpio.inc
@@ -83,7 +83,7 @@ GPIO(USB_C1_PD_RST, PIN(0, 0), GPIO_OUT_LOW) /* C1 PD Reset */
GPIO(USB_C0_DP_HPD, PIN(9, 4), GPIO_INPUT) /* C0 DP Hotplug Detect */
GPIO(USB_C1_DP_HPD, PIN(A, 5), GPIO_INPUT) /* C1 DP Hotplug Detect */
GPIO(USB_PP3300_USB_PD, PIN(8, 4), GPIO_INPUT) /* Reserved. Currently, has no effect. */
-GPIO(USB2_ID, PIN(4, 2), GPIO_OUT_LOW) /* USB OTG ID */
+GPIO(USB2_ID, PIN(4, 2), GPIO_OUT_HIGH) /* USB OTG ID */
GPIO(USB3_POWER_DOWN_L, PIN(3, 2), GPIO_OUT_LOW) /* USB3 Redriver Power control. Only used by Sona. */
/* Sensors */
diff --git a/board/nami/usb_pd_policy.c b/board/nami/usb_pd_policy.c
index 295f6f9c60..f4ad8afead 100644
--- a/board/nami/usb_pd_policy.c
+++ b/board/nami/usb_pd_policy.c
@@ -166,8 +166,7 @@ void pd_execute_data_swap(int port, int data_role)
if (port != 0)
return;
- gpio_set_level(GPIO_USB2_ID,
- (data_role == PD_ROLE_UFP) ? 1 : 0);
+ gpio_set_level(GPIO_USB2_ID, (data_role == PD_ROLE_UFP) ? 0 : 1);
}
void pd_check_pr_role(int port, int pr_role, int flags)