summaryrefslogtreecommitdiff
path: root/board/nami_fp
diff options
context:
space:
mode:
authorTom Hughes <tomhughes@chromium.org>2019-01-29 11:20:57 -0800
committerchrome-bot <chrome-bot@chromium.org>2019-02-06 19:32:42 -0800
commit4dfbfc9f0092312613aaa5d932b5e74d21a74069 (patch)
tree17588d94c54501ef10d37aea97396c24de8ef95a /board/nami_fp
parente411cb7a70b25455d4f487de78e5dca100de9bf9 (diff)
downloadchrome-ec-4dfbfc9f0092312613aaa5d932b5e74d21a74069.tar.gz
flash_fp_mcu: add option (-r) to read from FPMCU
This is useful for debugging and will also be used in the automated tests to validate RDP1. BRANCH=nocturne,nami BUG=chromium:890059 TEST=dut-control fw_wp_state:force_off flash_fp_mcu /opt/google/biod/fw/nocturne_fp_v2.2.110-b936c0a3c.bin ectool --name=cros_fp version flash_fp_mcu -r rb.bin diff rb.in /opt/google/biod/fw/nocturne_fp_v2.2.110-b936c0a3c.bin CQ-DEPEND=Iaf56d202828d58e855e567d3cd859f02a1996e09 Change-Id: Ieeb60e97df72093bec01b240782b902d8d0674d6 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1443857 Reviewed-by: Nicolas Norvez <norvez@chromium.org>
Diffstat (limited to 'board/nami_fp')
-rwxr-xr-xboard/nami_fp/flash_fp_mcu83
1 files changed, 15 insertions, 68 deletions
diff --git a/board/nami_fp/flash_fp_mcu b/board/nami_fp/flash_fp_mcu
index e7adeb017e..8beff69460 100755
--- a/board/nami_fp/flash_fp_mcu
+++ b/board/nami_fp/flash_fp_mcu
@@ -3,86 +3,33 @@
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.
+. /usr/share/flash_fp_mcu/flash_fp_mcu_common.sh
+
# Kabylake PCH GPIOs
-KBL_GPIOCHIP="gpiochip360"
+readonly KBL_GPIOCHIP="gpiochip360"
if [[ -e "/sys/class/gpio/${KBL_GPIOCHIP}" ]]; then
# Ekko configuration
echo "NOTE: For use with updating FP MCU on NAMI boards only"
- SPIDEV="/dev/spidev32765.0"
+ readonly SPIDEV="/dev/spidev32765.0"
# GSPI1 ACPI device for FP MCU
- SPIID="spi-PRP0001:02"
+ readonly SPIID="spi-PRP0001:02"
# FPMCU RST_ODL is on GPP_C9 = 360 + 57 = 417
- GPIO_NRST=417
+ readonly GPIO_NRST=417
# FPMCU BOOT0 is on GPP_D5 = 360 + 77 = 437
- GPIO_BOOT0=437
+ readonly GPIO_BOOT0=437
# FP_PWR_EN is on GPP_B11 = 360 + 35 = 395
- GPIO_PWREN=395
+ readonly GPIO_PWREN=395
else
echo "Cannot find a known GPIO chip."
exit 1
fi
-if [[ ! -f "$1" ]]; then
- echo "Invalid image file: $1"
- echo "Usage: $0 ec.bin"
- exit 1
-fi
-
-if ectool gpioget EC_WP_L | grep -q '= 0'; then
- echo "Please make sure WP is deasserted."
- exit 1
-fi
-
-# Ensure the ACPI is not cutting power when unloading cros-ec-spi
-echo ${GPIO_PWREN} > /sys/class/gpio/export
-echo "out" > /sys/class/gpio/gpio${GPIO_PWREN}/direction
-echo 1 > /sys/class/gpio/gpio${GPIO_PWREN}/value
-
-# Remove cros_fp if present
-echo "${SPIID}" > /sys/bus/spi/drivers/cros-ec-spi/unbind
-
-# Configure the MCU Boot0 and NRST GPIOs
-echo ${GPIO_BOOT0} > /sys/class/gpio/export
-echo "out" > /sys/class/gpio/gpio${GPIO_BOOT0}/direction
-echo ${GPIO_NRST} > /sys/class/gpio/export
-echo "out" > /sys/class/gpio/gpio${GPIO_NRST}/direction
-
-# Reset sequence to enter bootloader mode
-echo 1 > /sys/class/gpio/gpio${GPIO_BOOT0}/value
-echo 0 > /sys/class/gpio/gpio${GPIO_NRST}/value
-sleep 0.001
-
-# load spidev (fail on cros-ec-spi first to change modalias)
-echo "${SPIID}" > /sys/bus/spi/drivers/cros-ec-spi/bind 2>/dev/null
-echo "${SPIID}" > /sys/bus/spi/drivers/spidev/bind
-
-# Release reset as the SPI bus is now ready
-echo 1 > /sys/class/gpio/gpio${GPIO_NRST}/value
-echo "in" > /sys/class/gpio/gpio${GPIO_NRST}/direction
-
-stm32mon -U -u -p -s ${SPIDEV} -e -w $1
-
-# unload spidev
-echo "${SPIID}" > /sys/bus/spi/drivers/spidev/unbind
-
-# Go back to normal mode
-echo "out" > /sys/class/gpio/gpio${GPIO_NRST}/direction
-echo 0 > /sys/class/gpio/gpio${GPIO_BOOT0}/value
-echo 0 > /sys/class/gpio/gpio${GPIO_NRST}/value
-echo 1 > /sys/class/gpio/gpio${GPIO_NRST}/value
-
-# Give up GPIO control
-echo "in" > /sys/class/gpio/gpio${GPIO_BOOT0}/direction
-echo "in" > /sys/class/gpio/gpio${GPIO_NRST}/direction
-echo ${GPIO_BOOT0} > /sys/class/gpio/unexport
-echo ${GPIO_NRST} > /sys/class/gpio/unexport
+flash_fp_mcu_stm32 \
+ "${SPIDEV}" \
+ "${SPIID}" \
+ "${GPIO_NRST}" \
+ "${GPIO_BOOT0}" \
+ "${GPIO_PWREN}" \
+ "${1}"
-# wait for FP MCU to come back up (including RWSIG delay)
-sleep 2
-# Put back cros_fp driver
-echo "${SPIID}" > /sys/bus/spi/drivers/cros-ec-spi/bind
-# Kernel driver is back, we are no longer controlling power
-echo ${GPIO_PWREN} > /sys/class/gpio/unexport
-# Test it
-ectool --name=cros_fp version