meowth: remove meowth/zoombini overlays and repositories

BRANCH=none
BUG=b:118494679
TEST=Verify PreCQ build

Signed-off-by: Bob Moragues <moragues@chromium.org>

Change-Id: Id6889d922a2b4d812cc92ddbb35b2581d881459d
Reviewed-on: https://chromium-review.googlesource.com/1354316
Commit-Ready: Bob Moragues <moragues@chromium.org>
Tested-by: Bob Moragues <moragues@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>

8 files changed, 459 insertions, 1 deletions

diff --git a/board/nocturne_fp b/board/nocturne_fp
deleted file mode 120000
index 643a606728..0000000000
--- a/board/nocturne_fp
+++ /dev/null
@@ -1 +0,0 @@
-meowth_fp
\ No newline at end of file
diff --git a/board/nocturne_fp/board.c b/board/nocturne_fp/board.c
new file mode 100644
index 0000000000..84f6ae9445
--- /dev/null
+++ b/board/nocturne_fp/board.c
@@ -0,0 +1,82 @@
+/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* Meowth Fingerprint MCU configuration */
+
+#include "common.h"
+#include "console.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "registers.h"
+#include "spi.h"
+#include "system.h"
+#include "task.h"
+#include "util.h"
+
+#ifndef HAS_TASK_FPSENSOR
+void fps_event(enum gpio_signal signal)
+{
+}
+#endif
+
+static void ap_deferred(void)
+{
+	/*
+	 * in S3:   SLP_S3_L is 0 and SLP_S0_L is X.
+	 * in S0ix: SLP_S3_L is X and SLP_S0_L is 0.
+	 * in S0:   SLP_S3_L is 1 and SLP_S0_L is 1.
+	 * in S5/G3, the FP MCU should not be running.
+	 */
+	int running = gpio_get_level(GPIO_PCH_SLP_S3_L)
+			&& gpio_get_level(GPIO_PCH_SLP_S0_L);
+
+	if (running) { /* S0 */
+		disable_sleep(SLEEP_MASK_AP_RUN);
+		hook_notify(HOOK_CHIPSET_RESUME);
+	} else { /* S0ix/S3 */
+		hook_notify(HOOK_CHIPSET_SUSPEND);
+		enable_sleep(SLEEP_MASK_AP_RUN);
+	}
+}
+DECLARE_DEFERRED(ap_deferred);
+
+/* PCH power state changes */
+void slp_event(enum gpio_signal signal)
+{
+	hook_call_deferred(&ap_deferred_data, 0);
+}
+
+#include "gpio_list.h"
+
+/* SPI devices */
+const struct spi_device_t spi_devices[] = {
+	/* Fingerprint sensor (SCLK at 4Mhz) */
+	{ CONFIG_SPI_FP_PORT, 3, GPIO_SPI4_NSS }
+};
+const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
+
+static void spi_configure(void)
+{
+	/* Configure SPI GPIOs */
+	gpio_config_module(MODULE_SPI_MASTER, 1);
+	/* Set all SPI master signal pins to very high speed: pins E2/4/5/6 */
+	STM32_GPIO_OSPEEDR(GPIO_E) |= 0x00003f30;
+	/* Enable clocks to SPI4 module (master) */
+	STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI4;
+
+	spi_enable(CONFIG_SPI_FP_PORT, 1);
+}
+
+/* Initialize board. */
+static void board_init(void)
+{
+	spi_configure();
+
+	/* Enable interrupt on PCH power signals */
+	gpio_enable_interrupt(GPIO_PCH_SLP_S3_L);
+	gpio_enable_interrupt(GPIO_PCH_SLP_S0_L);
+	/* enable the SPI slave interface if the PCH is up */
+	hook_call_deferred(&ap_deferred_data, 0);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/nocturne_fp/board.h b/board/nocturne_fp/board.h
new file mode 100644
index 0000000000..5d3807c709
--- /dev/null
+++ b/board/nocturne_fp/board.h
@@ -0,0 +1,167 @@
+/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Meowth Fingerprint MCU configuration */
+
+#ifndef __BOARD_H
+#define __BOARD_H
+
+/*
+ * TODO(b/73337313) remove this config,
+ * once the write-protection scheme is decided and validated.
+ */
+#define CONFIG_SYSTEM_UNLOCKED
+
+/*
+ * Flash layout: we redefine the sections offsets and sizes as we want to
+ * include a rollback region, and will use RO/RW regions of different sizes.
+ */
+#undef _IMAGE_SIZE
+#undef CONFIG_ROLLBACK_OFF
+#undef CONFIG_ROLLBACK_SIZE
+#undef CONFIG_FLASH_PSTATE
+#undef CONFIG_FW_PSTATE_SIZE
+#undef CONFIG_FW_PSTATE_OFF
+#undef CONFIG_SHAREDLIB_SIZE
+#undef CONFIG_RO_MEM_OFF
+#undef CONFIG_RO_STORAGE_OFF
+#undef CONFIG_RO_SIZE
+#undef CONFIG_RW_MEM_OFF
+#undef CONFIG_RW_STORAGE_OFF
+#undef CONFIG_RW_SIZE
+#undef CONFIG_EC_PROTECTED_STORAGE_OFF
+#undef CONFIG_EC_PROTECTED_STORAGE_SIZE
+#undef CONFIG_EC_WRITABLE_STORAGE_OFF
+#undef CONFIG_EC_WRITABLE_STORAGE_SIZE
+#undef CONFIG_WP_STORAGE_OFF
+#undef CONFIG_WP_STORAGE_SIZE
+
+#define CONFIG_SHAREDLIB_SIZE   0
+
+#define CONFIG_RO_MEM_OFF       0
+#define CONFIG_RO_STORAGE_OFF   0
+#define CONFIG_RO_SIZE          (768*1024)
+
+/* EC rollback protection block */
+#define CONFIG_ROLLBACK_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
+#define CONFIG_ROLLBACK_SIZE (CONFIG_FLASH_BANK_SIZE * 2)
+
+#define CONFIG_RW_MEM_OFF	(CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE)
+#define CONFIG_RW_STORAGE_OFF	0
+#define CONFIG_RW_SIZE		(CONFIG_FLASH_SIZE -			\
+				(CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF))
+
+#define CONFIG_EC_PROTECTED_STORAGE_OFF         CONFIG_RO_MEM_OFF
+#define CONFIG_EC_PROTECTED_STORAGE_SIZE        CONFIG_RO_SIZE
+#define CONFIG_EC_WRITABLE_STORAGE_OFF          CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE         CONFIG_RW_SIZE
+
+#define CONFIG_WP_STORAGE_OFF           CONFIG_EC_PROTECTED_STORAGE_OFF
+#define CONFIG_WP_STORAGE_SIZE          CONFIG_EC_PROTECTED_STORAGE_SIZE
+
+/*
+ * We want to prevent flash readout, and use it as indicator of protection
+ * status.
+ */
+#define CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE
+
+/* the UART console is on USART1 */
+#undef CONFIG_UART_CONSOLE
+#define CONFIG_UART_CONSOLE 1
+#define CONFIG_UART_TX_DMA
+#define CONFIG_UART_TX_DMA_PH DMAMUX1_REQ_USART1_TX
+#undef CONFIG_UART_TX_BUF_SIZE
+#define CONFIG_UART_TX_BUF_SIZE 2048
+
+/* Optional features */
+#undef CONFIG_ADC
+#define CONFIG_CMD_IDLE_STATS
+#define CONFIG_DMA
+#define CONFIG_FORCE_CONSOLE_RESUME
+#define CONFIG_FPU
+#undef CONFIG_HIBERNATE
+#define CONFIG_HOST_COMMAND_STATUS
+#undef CONFIG_I2C
+#undef CONFIG_LID_SWITCH
+#define CONFIG_LOW_POWER_IDLE
+#define CONFIG_MKBP_EVENT
+#define CONFIG_PRINTF_LEGACY_LI_FORMAT
+#define CONFIG_SHA256
+#define CONFIG_SHA256_UNROLLED
+#define CONFIG_SPI
+#define CONFIG_STM_HWTIMER32
+#define CONFIG_SUPPRESSED_HOST_COMMANDS \
+	EC_CMD_CONSOLE_SNAPSHOT, EC_CMD_CONSOLE_READ, EC_CMD_PD_GET_LOG_ENTRY
+#undef CONFIG_TASK_PROFILING
+#define CONFIG_WATCHDOG_HELP
+#define CONFIG_WP_ACTIVE_HIGH
+
+/* SPI configuration for the fingerprint sensor */
+#define CONFIG_SPI_MASTER
+#define CONFIG_SPI_FP_PORT  2 /* SPI4: third master config */
+#ifdef SECTION_IS_RW
+#define CONFIG_FP_SENSOR_FPC1145
+#define CONFIG_CMD_FPSENSOR_DEBUG
+/*
+ * Use the malloc code only in the RW section (for the private library),
+ * we cannot enable it in RO since it is not compatible with the RW verification
+ * (shared_mem_init done too late).
+ */
+#define CONFIG_MALLOC
+/* Special memory regions to store large arrays */
+#define FP_FRAME_SECTION    __SECTION(ahb4)
+#define FP_TEMPLATE_SECTION __SECTION(ahb)
+
+#else /* SECTION_IS_RO */
+/* RO verifies the RW partition signature */
+#define CONFIG_RSA
+#define CONFIG_RSA_KEY_SIZE 3072
+#define CONFIG_RSA_EXPONENT_3
+#define CONFIG_RWSIG
+#endif
+#define CONFIG_RWSIG_TYPE_RWSIG
+
+/* RW does slow compute, RO does slow flash erase. */
+#undef CONFIG_WATCHDOG_PERIOD_MS
+#define CONFIG_WATCHDOG_PERIOD_MS 10000
+
+/*
+ * Add rollback protection
+ */
+#define CONFIG_ROLLBACK
+#define CONFIG_ROLLBACK_SECRET_SIZE 32
+
+#define CONFIG_ROLLBACK_MPU_PROTECT
+
+/*
+ * We do not use any "locally" generated entropy: this is normally used
+ * to add local entropy when the main source of entropy is remote.
+ */
+#undef CONFIG_ROLLBACK_SECRET_LOCAL_ENTROPY_SIZE
+#ifdef SECTION_IS_RW
+#undef CONFIG_ROLLBACK_UPDATE
+#endif
+
+#define CONFIG_AES
+#define CONFIG_AES_GCM
+
+#define CONFIG_RNG
+
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_SPI_XFER
+
+#ifndef __ASSEMBLER__
+
+/* Timer selection */
+#define TIM_CLOCK32 2
+#define TIM_WATCHDOG 16
+
+#include "gpio_signal.h"
+
+void fps_event(enum gpio_signal signal);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __BOARD_H */
diff --git a/board/nocturne_fp/build.mk b/board/nocturne_fp/build.mk
new file mode 100644
index 0000000000..2c7a5d3d73
--- /dev/null
+++ b/board/nocturne_fp/build.mk
@@ -0,0 +1,14 @@
+# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+
+# the IC is STmicro STM32H743
+CHIP:=stm32
+CHIP_FAMILY:=stm32h7
+CHIP_VARIANT:=stm32h7x3
+
+board-y=board.o
+
+test-list-y=aes sha256 sha256_unrolled
diff --git a/board/nocturne_fp/dev_key.pem b/board/nocturne_fp/dev_key.pem
new file mode 100644
index 0000000000..35c0035b20
--- /dev/null
+++ b/board/nocturne_fp/dev_key.pem
@@ -0,0 +1,39 @@
+-----BEGIN RSA PRIVATE KEY-----
+MIIG4wIBAAKCAYEAoxINZU5fQAiABFm4xT83HUQx/WvRlyZ3ZfRqTyMlMxw7U0cU
+DEw7fOY0oj20bkpmVJRfwkm4k7BwOuTt3nl5UuKgeztL4gW+h++ptIIzfT2/a4KL
+BnHsuNfgXZ+yzJ5RSKlJwVOibJr5CNfsmESX4Lwe3LudFc7iE/yfgsOyU/9Ha/jB
+mgLywyWObwpfAt+viOCIF4mYeEI5bLpDHqwk6EnEq0jWaNpcEsLA/twhDf2Qxc7I
+7Zds3f6C3iA1N/d0Zmva4UvdAGnFzQlq9mmgnCenIjwEb4jxqcFXaMgk88jkcheY
+q7MQANRt+iYOX2MiUNtigUoDoJTMBiV3bRs47sSiH+lS6hZHdOsmjMyF30bV5IJD
+k+x1Zoxsd2jYR1PXgxZ+pxLoKx/m9KIV8onbqgl0Jx4+JkABH5eYp/KAhObCenLS
+CySFi7OLbi915yydzFJ3C34pgWVN077GVCXGqglxDcNMacqXqHCwOUoNuAGXjxyF
+XH33G9a/TJDzQhZFAgEDAoIBgGy2s5je6iqwVVg70IN/ehOCy/5H4Q9u+kP4Rt9s
+w3doJ4zaDV2IJ6iZeGwpIvQxmY24P9bb0GJ1oCdDST77pjdBwFInh+wD1FqfxnhW
+zP4pKkesXK72ndCP6ukVId2+4NsbhoDibEhnULCP8xAtupXSvz3SaLk0lrf9v6yC
+duKqL51QgRFXTIIZCZ9cP1c/yltAWrpbuvrW0PMm12nIGJrb2HIwjvCRkrcsgKno
+FglTtdk0hfO6SJP/AelqziVPod5DxP4Gcws0JWnWjIKtYmNpIrI/sfVD29DNLYYS
+Pn1Vgxi5UcwfEbcxkwxMKoJOUb1WSPkvjpQTlQUPiBLX3sLpLvxaOVrEjNXy+V13
+Jl7bc2dGbDIsQMXkFiodTHsqwAq1diFOUL9oE6VeES2hmX63f7lHSXMb92phmvs4
+BylzoTK64ew8oUkufLTX/ys0LGiGvPXCrdfDxdsO2Rx90XB5YPcvvQKge0eCfDck
+kCX4C/6j7V3y/nS5GzpLCFshqwKBwQDVaKdjlpzAKKu+hfBRaujZsrgXd2i4LTuI
+r+sclHl4aII0HJbSolsiV8Pc+jcFtvzLDUnSh4Pjza/6qtYF0q3fxAXQCmBAq8Xc
+AF2sYmZJmMT4OajMS0LG7nhYgm5OpXpyvgc+ndBnDtqXVPQy/wpo8dBV8G1QtXbj
+OsvrTeQ8ZaFcUA4jOuyz+VNpONOUzvxx/jVwuEDVl7xB5/6TayNbCrecqd6CsSur
+S3Z21lelrCV/CjIJqkPZQlgwsKE31CUCgcEAw52MAKuTr3Lh78Gn4PqkLVc6/2UQ
+x3XsZ92oAxhNv2AdmOUHJuIaS7JNirmXljaq6cyrOPsp3qm8g+NVSwS86qLV1Vec
+oUOuV/5S1DdmB2Tj0V74fF7RdsfS37p3P+49AEhGNn+epPTu5UAH+xhrAwRkO0Li
+qOCXHMpkQ9CRilOvUgpxBY6m6fR89bKjkY9evYomKiHj6CfoyUCCFf3pJkin/lHS
+YyizEeF/b7zd2WFgEhxvRec1k36+RG/FgY+hAoHBAI5FxO0PEyrFx9RZSuDx8JEh
+0A+k8HrI0lsf8hMNplBFrCK9ueHBkhblLT38JK55/dyzhoxaV+0zyqccjq6Mc+qC
+roqxlYByg+gAPnLsRDEQg1AmcIgyLISe+uWsSYnDpvcpWim+iu9fPGTjTXdUsZtL
+4DlK84sjpJd8h/Iz7X2ZFj2KtBd8nc1Q4kYl4mM0qEv+zkslgI5lKCvv/wzyF5IH
+JRMb6ax2HRzc+aSO5RkdblSxdrEcLTuBkCB1wM/iwwKBwQCCaQgAcmJ090FKgRqV
+/G1zj3yqQ2CE+UhFPnACEDPU6r5l7gTElrwydt5ce7pkJHHxMxzQp3E/G9MCl44y
+AyicbI6OOmhrgnQ6qYyNekQE7e02P1BS6eD52oyVJvoqntNVhYQkVRRt+J9DgAVS
+EEdXWELSLJcbQGS93ELX4GEG4nThXEtZCcSb+FNOdxe2X5R+XBlxa+1Fb/CGKwFj
+/ptu2xqpi+GXcHdhQP+f0z6Q65VhaEoumiO3qdQtn9kBCmsCgcEA0/VwBz03FMcv
+2SM6zDbL2Kf4PnnLJuDHFzItWH8smrBNVfOOuJ5KGhuIHAAJxaQoWBxeYeaPPqme
+5rQRl58XEb5h3FswAKPx2U77NUROtObOVffV5Tid1E+iBQYhlUUkxtE5b+Said3u
+LqkP8K5n1ai2xuvHusuL6vcp/5T+WrSG5GDiGU+27c2Uf/NePbFYggLl3P9rmDM8
+/1xGGpxMGV2OrOhXtPk7LykEdJRuN+7YhNX5dW1LwWcicOLkFVOG
+-----END RSA PRIVATE KEY-----
diff --git a/board/nocturne_fp/ec.tasklist b/board/nocturne_fp/ec.tasklist
new file mode 100644
index 0000000000..6dfaaeff14
--- /dev/null
+++ b/board/nocturne_fp/ec.tasklist
@@ -0,0 +1,24 @@
+/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * List of enabled tasks in the priority order
+ *
+ * The first one has the lowest priority.
+ *
+ * For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
+ * TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
+ * where :
+ * 'n' in the name of the task
+ * 'r' in the main routine of the task
+ * 'd' in an opaque parameter passed to the routine at startup
+ * 's' is the stack size in bytes; must be a multiple of 8
+ */
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS_RO(RWSIG, rwsig_task, NULL, 1280) \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, 1024) \
+	TASK_ALWAYS_RW(FPSENSOR, fp_task, NULL, 4096) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 4096) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/nocturne_fp/flash_fp_mcu b/board/nocturne_fp/flash_fp_mcu
new file mode 100755
index 0000000000..7f5a566c13
--- /dev/null
+++ b/board/nocturne_fp/flash_fp_mcu
@@ -0,0 +1,102 @@
+#!/bin/sh
+# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Cannonlake PCH GPIOs
+CNL_GPIOCHIP="gpiochip268"
+# Kabylake PCH GPIOs
+KBL_GPIOCHIP="gpiochip360"
+
+if [ -e "/sys/class/gpio/${CNL_GPIOCHIP}" ]; then
+	# Meowth configuration
+
+	SPIDEV="/dev/spidev1.0"
+	# GSPI1 ACPI device for FP MCU
+	SPIID="spi-PRP0001:01"
+	# FPMCU RST_ODL is on GPP_A23 = 268 + 23 = 291
+	GPIO_NRST=291
+	# FPMCU BOOT0 is on GPP_A21 = 268 + 21 = 289
+	GPIO_BOOT0=289
+	# FP_PWR_EN is on GPP_A11 = 268 + 11 = 279
+	GPIO_PWREN=279
+elif [ -e "/sys/class/gpio/${KBL_GPIOCHIP}" ]; then
+	# Nocturne configuration
+
+	SPIDEV="/dev/spidev32765.0"
+	# GSPI1 ACPI device for FP MCU
+	SPIID="spi-PRP0001:02"
+	# FPMCU RST_ODL is on GPP_C10 = 360 + 58 = 418
+	GPIO_NRST=418
+	# FPMCU BOOT0 is on GPP_C8 = 360 + 56 = 416
+	GPIO_BOOT0=416
+	# FP_PWR_EN is on GPP_A11 = 360 + 11 = 371
+	GPIO_PWREN=371
+else
+	echo "Cannot find a known GPIO chip."
+	exit 1
+fi
+
+if [ ! -f "$1" ]; then
+	echo "Invalid image file: $1"
+	echo "Usage: $0 ec.bin"
+	exit 1
+fi
+
+if ectool gpioget EC_WP_L | grep -q '= 0'; then
+	echo "Please make sure WP is deasserted."
+	exit 1
+fi
+
+# Ensure the ACPI is not cutting power when unloading cros-ec-spi
+echo ${GPIO_PWREN} > /sys/class/gpio/export
+echo "out" > /sys/class/gpio/gpio${GPIO_PWREN}/direction
+echo 1 > /sys/class/gpio/gpio${GPIO_PWREN}/value
+
+# Remove cros_fp if present
+echo "${SPIID}" > /sys/bus/spi/drivers/cros-ec-spi/unbind
+
+# Configure the MCU Boot0 and NRST GPIOs
+echo ${GPIO_BOOT0} > /sys/class/gpio/export
+echo "out" > /sys/class/gpio/gpio${GPIO_BOOT0}/direction
+echo ${GPIO_NRST} > /sys/class/gpio/export
+echo "out" > /sys/class/gpio/gpio${GPIO_NRST}/direction
+
+# Reset sequence to enter bootloader mode
+echo 1 > /sys/class/gpio/gpio${GPIO_BOOT0}/value
+echo 0 > /sys/class/gpio/gpio${GPIO_NRST}/value
+sleep 0.001
+
+# load spidev (fail on cros-ec-spi first to change modalias)
+echo "${SPIID}" > /sys/bus/spi/drivers/cros-ec-spi/bind 2>/dev/null
+echo "${SPIID}" > /sys/bus/spi/drivers/spidev/bind
+
+# Release reset as the SPI bus is now ready
+echo 1 > /sys/class/gpio/gpio${GPIO_NRST}/value
+echo "in" > /sys/class/gpio/gpio${GPIO_NRST}/direction
+
+stm32mon -U -u -p -s ${SPIDEV} -e -w $1
+
+# unload spidev
+echo "${SPIID}" > /sys/bus/spi/drivers/spidev/unbind
+
+# Go back to normal mode
+echo "out" > /sys/class/gpio/gpio${GPIO_NRST}/direction
+echo 0 > /sys/class/gpio/gpio${GPIO_BOOT0}/value
+echo 0 > /sys/class/gpio/gpio${GPIO_NRST}/value
+echo 1 > /sys/class/gpio/gpio${GPIO_NRST}/value
+
+# Give up GPIO control
+echo "in" > /sys/class/gpio/gpio${GPIO_BOOT0}/direction
+echo "in" > /sys/class/gpio/gpio${GPIO_NRST}/direction
+echo ${GPIO_BOOT0} > /sys/class/gpio/unexport
+echo ${GPIO_NRST} > /sys/class/gpio/unexport
+
+# wait for FP MCU to come back up (including RWSIG delay)
+sleep 2
+# Put back cros_fp driver
+echo "${SPIID}" > /sys/bus/spi/drivers/cros-ec-spi/bind
+# Kernel driver is back, we are no longer controlling power
+echo ${GPIO_PWREN} > /sys/class/gpio/unexport
+# Test it
+ectool --name=cros_fp version
diff --git a/board/nocturne_fp/gpio.inc b/board/nocturne_fp/gpio.inc
new file mode 100644
index 0000000000..e0470b2cb6
--- /dev/null
+++ b/board/nocturne_fp/gpio.inc
@@ -0,0 +1,31 @@
+/*
+ * Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Interrupts */
+GPIO_INT(FPS_INT,         PIN(A, 0), GPIO_INT_RISING, fps_event)
+GPIO_INT(SPI1_NSS,        PIN(A, 4), GPIO_INPUT, spi_event)
+
+GPIO_INT(PCH_SLP_S0_L,    PIN(D,13), GPIO_INT_BOTH, slp_event)
+GPIO_INT(PCH_SLP_S3_L,    PIN(A,11), GPIO_INT_BOTH, slp_event)
+GPIO(PCH_SLP_S4_L,        PIN(D, 8), GPIO_INPUT)
+GPIO(PCH_SLP_SUS_L,       PIN(D, 3), GPIO_INPUT)
+
+GPIO(WP,                  PIN(B, 7), GPIO_INPUT)
+
+/* Outputs */
+GPIO(EC_INT_L,            PIN(A, 1),  GPIO_OUT_HIGH)
+GPIO(FP_RST_ODL,          PIN(E, 0),  GPIO_OUT_HIGH)
+GPIO(SPI4_NSS,            PIN(E, 4),  GPIO_OUT_HIGH)
+GPIO(USER_PRES_L,         PIN(C, 5),  GPIO_ODR_HIGH)
+
+UNIMPLEMENTED(ENTERING_RW)
+
+/* USART1: PA9/PA10 */
+ALTERNATE(PIN_MASK(A, 0x0600), GPIO_ALT_USART,  MODULE_UART, GPIO_PULL_UP)
+/* SPI1 slave from the AP: PA4/5/6/7 */
+ALTERNATE(PIN_MASK(A, 0x00f0), GPIO_ALT_SPI, MODULE_SPI,  0)
+/* SPI4 master to sensor: PE2/5/6 */
+ALTERNATE(PIN_MASK(E, 0x0064), GPIO_ALT_SPI, MODULE_SPI_MASTER,  0)