diff options
| author | Mulin Chao <mlchao@nuvoton.com> | 2017-05-24 17:51:42 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-06-09 21:44:06 -0700 |
| commit | a08d004e97e3bd6fe232b5f050bad2c448f381c0 (patch) | |
| tree | df87cceb5389560e70bde1c68f60b95e8e433548 /board/npcx7_evb/board.h | |
| parent | e9215ba711d337e4cfc9524c4ef07b03a813c8fb (diff) | |
| download | chrome-ec-a08d004e97e3bd6fe232b5f050bad2c448f381c0.tar.gz | |
npcx: clock: Add support for external 32kHz crystal osc.
In this CL, we add selecting LFCLK sources functionality for npcx7 ec
series. (Please notice not all of npcx7 ec series support this feature.)
Beside internal LFCLK source, ec also can choose the external 32kHz
crystal oscillator as LFCLK source for the specific application. We also
introduce a new definition, CONFIG_CLOCK_SRC_EXTERNAL, to switch this
feature in the board level driver.
This CL also adds:
1. LFCG register definitions in registers.h.
2. Change the order of each npcx modules by memory address.
BRANCH=none
BUG=none
TEST=Output LFCLK source through GPIO75. Compare with external 32kHz
crystal osc. on npcx7_evb and make sure the sources are the same.
Change-Id: I137146bf51ccb51266b9aac1e2e28bcea87dc4f5
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/520745
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'board/npcx7_evb/board.h')
| -rw-r--r-- | board/npcx7_evb/board.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/board/npcx7_evb/board.h b/board/npcx7_evb/board.h index 1b00a4715a..0c93999497 100644 --- a/board/npcx7_evb/board.h +++ b/board/npcx7_evb/board.h @@ -57,6 +57,7 @@ /* New features on npcx7 ec */ #define CONFIG_KEYBOARD_KSO_HIGH_DRIVE /* Quasi-bidirectional buf for KSOs */ #undef CONFIG_HIBERNATE_PSL /* Use PSL (Power Switch Logic) for hibernate */ +#undef CONFIG_CLOCK_SRC_EXTERNAL /* Use external 32kHz OSC as LFCLK source */ /* Optional feature to configure npcx7 chip */ #define NPCX_UART_MODULE2 0 /* 0:GPIO10/11 1:GPIO64/65 as UART */ |