npcx: Use SPI status register instead of pstate

The npcx chip and evb use a SPI flash chip to hold the EC image.  They
don't need pstate, and should use the SPI flash status register
directly.

1. Remove CONFIG_FLASH_PSTATE from npcx_evb.
2. Remap WP_L GPIO to GPIO 93 (this should be the same as the write protect
   line to the SPI flash chip).
3. Change the npcx flash driver so that it directly reads/writes the SPI
   status register instead of mucking with pstate.

BUG=chrome-os-partner:34346
BRANCH=none
TEST=manual
   Add a switch or jumper to the EVB so R1 can be closed.
   Toggle the switch and see that WP_L state changes.  Leave enabled.
   flashinfo -> nothing is protected, WP_L is enabled (=0)
      (also do this after each flashwp command to check the protection status)
   flashwp enable -> RO is protected now and at boot.
   reboot
   flashwp enable -> RO is still protected.
   flashwp disable -> RO is still protected. (because WP switch is enabled).
   Toggle the switch so WP_L is disabled (=1)
   flashwp disable -> Succeeds, flash is not protected

Change-Id: Ifa959bce69f8eb4724057ecaa6a6c5075783c19d
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/253633
Reviewed-by: Shawn N <shawnn@chromium.org>

0 files changed, 0 insertions, 0 deletions