diff options
| author | Ian Chao <mlchao@nuvoton.com> | 2014-12-06 14:23:02 +0800 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-01-14 03:16:10 +0000 |
| commit | 4ee50837a0263a5bfcb61e32a862797ede387c78 (patch) | |
| tree | af86c4bd09ff9e4d364ff66444a26f9091b15d14 /board/npcx_evb/gpio.inc | |
| parent | 3951165fe9182cb6c9981d0a69c36765c7fe8916 (diff) | |
| download | chrome-ec-4ee50837a0263a5bfcb61e32a862797ede387c78.tar.gz | |
nuc: Add all IC specific drivers of NPCX5M5G
Add npcx_evb in board folder for testing
Add shared-spi arch support in common layer.
Modified drivers for
1. Fan.c: console command “pwmduty”.
2. Pwm.c: for the issue when set duty to 0.
3. System.c: for hw reset only during system reset.
4. Flash.c: Fixed access denied bug of the flash driver for host command.
5. Comments from Patch Set 1
6. Comments from Patch Set 3 (except sha256.c)
7. Add openocd and flash_ec support for npcx_evb
8. Add little FW and spi-flash upload FW in chip folder
9. Add optional make rules for PROJECT_EXTRA
10.Replace CONFIG_SHRSPI_ARCH with CONFIG_CODERAM_ARCH and remove changes
in common layer sources for shared-spi arch. (except sysjump)
11.Find the root cause of JTAG issue and use workaround method
with SUPPORT_JTAG in clock.c
12 Execute hibernate in low power RAM for better power consumption
13 Add workaround method for version console command
14 Modified coding style issues by checkpatch.pl tool
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I5e383420642de1643e2bead837a55c8c58481786
Signed-off-by: Ian Chao <mlchao@nuvoton.com>
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/233742
Diffstat (limited to 'board/npcx_evb/gpio.inc')
| -rw-r--r-- | board/npcx_evb/gpio.inc | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/board/npcx_evb/gpio.inc b/board/npcx_evb/gpio.inc new file mode 100644 index 0000000000..08837dfea1 --- /dev/null +++ b/board/npcx_evb/gpio.inc @@ -0,0 +1,45 @@ +/* -*- mode:c -*- + * + * Copyright (c) 2014 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* TODO: Redefine debug 2 inputs */ +GPIO(RECOVERY_L, 0, 0, GPIO_PULL_UP | GPIO_INT_BOTH, switch_interrupt) /* Recovery signal from servo */ +GPIO(WP_L, 0, 1, GPIO_PULL_DOWN | GPIO_INT_BOTH, switch_interrupt) /* Write protect input */ + +/* For testing 8042 commands, we need the following GPIOs */ +/* TODO: Redefine 4 inputs */ +GPIO(POWER_BUTTON_L, 0, 2, GPIO_PULL_UP | GPIO_INT_BOTH, power_button_interrupt) /* Power button */ +GPIO(LID_OPEN, 3, 3, GPIO_PULL_DOWN | GPIO_INT_BOTH, lid_interrupt) /* Lid switch */ +GPIO(ENTERING_RW, 3, 6, GPIO_OUT_LOW, NULL) /* Indicate when EC is entering RW code */ +GPIO(PCH_WAKE_L, 5, 0, GPIO_OUT_HIGH, NULL) /* Wake signal output to PCH */ + +/* Used for module testing */ +GPIO(PGOOD_FAN, C, 7, GPIO_PULL_UP | GPIO_INPUT, NULL) /* Power Good for FAN test */ +GPIO(SPI_CS_L, A, 5, GPIO_OUT_HIGH, NULL) /* SPI_CS Ready, Low Active. */ + +/* + * I2C pins should be configured as inputs until I2C module is + * initialized. This will avoid driving the lines unintentionally. + */ +GPIO(MASTER_I2C_SCL, B, 5, GPIO_INPUT, NULL) +GPIO(MASTER_I2C_SDA, B, 4, GPIO_INPUT, NULL) + +/* Used for board version command */ +GPIO(BOARD_VERSION1, 6, 4, GPIO_INPUT, NULL) /* Board version stuffing resistor 1 */ +GPIO(BOARD_VERSION2, 6, 5, GPIO_INPUT, NULL) /* Board version stuffing resistor 2 */ +GPIO(BOARD_VERSION3, 6, 6, GPIO_INPUT, NULL) /* Board version stuffing resistor 3 */ + +/* Alternate pins for UART/I2C/ADC/SPI/PWM/MFT */ +ALTERNATE(1, 0x03, 1, MODULE_UART, 0) /* CR_SIN/SOUT GPIO10/11 */ +ALTERNATE(B, 0x30, 1, MODULE_I2C, 0) /* I2C0SDA/I2C0SCL GPIOB4/B5 */ +ALTERNATE(8, 0x80, 1, MODULE_I2C, 0) /* I2C1SDA GPIO87 */ +ALTERNATE(9, 0x07, 1, MODULE_I2C, 0) /* I2C1SCL/I2C2SDA/I2C2SCL GPIO90/91/92 */ +ALTERNATE(4, 0x38, 1, MODULE_ADC, 0) /* ADC GPIO45/44/43 */ +ALTERNATE(A, 0x0A, 1, MODULE_SPI, 0) /* SPIP_MOSI/SPIP_SCLK GPIOA3/A1 */ +ALTERNATE(9, 0x20, 1, MODULE_SPI, 0) /* SPIP_MISO GPIO95 */ +ALTERNATE(C, 0x04, 1, MODULE_PWM_KBLIGHT, 0) /* PWM1 for PWM/KBLIGHT Test GPIOC2 */ +ALTERNATE(C, 0x08, 1, MODULE_PWM_FAN, 0) /* PWM0 for PWM/FAN Test GPIOC3 */ +ALTERNATE(4, 0x01, 1, MODULE_PWM_FAN, 0) /* MFT-1/TA1_TACH1 for FAN Test GPIOD3 */ |