diff options
| author | Mulin Chao <mlchao@nuvoton.com> | 2017-04-10 13:31:29 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-04-18 23:33:20 -0700 |
| commit | 2a6d939e10b2449a16d627821ce6568ce05c1573 (patch) | |
| tree | fadb0ec53d3a0ab165d1d68deeba96cadb4f7d1d /board/npcx_evb_arm/board.h | |
| parent | 9b710e13cd2ef714ef656eb94383666f337f211e (diff) | |
| download | chrome-ec-2a6d939e10b2449a16d627821ce6568ce05c1573.tar.gz | |
npcx: gpio: Change second tachometer source from TB2 to TA2.
In npcx's fan driver, ec selected mode 5 and capturer A as tachometer's
input. Choosing TB2 as the second tachometer source is not correct since
we didn't initialize the registers for TB2. This patch modified the
second tachometer's input from TB2 to TA2 and passed the verification by
following changes.
1. Add the second fan settings in pwm_channels, fans, and mft_channels
arraies.
2. Modified ALTERNATE marco for pwm-type fans.
3. Set CONFIG_FAN from 1 to 2.
4. Set NPCX_TACH_SEL2 to 1 to test tachometer input 2. (ie.GPIO73/A6)
BRANCH=none
BUG=none
TEST=test dual fans with fanset command on npcx_evb and use faninfo for
verifying. Measure the actual rpm by scope.
Change-Id: Ia1af2732d9a64e24285d12371223eb0e77e53357
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/472310
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'board/npcx_evb_arm/board.h')
| -rw-r--r-- | board/npcx_evb_arm/board.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/npcx_evb_arm/board.h b/board/npcx_evb_arm/board.h index 932aa663f0..dae3af8fb0 100644 --- a/board/npcx_evb_arm/board.h +++ b/board/npcx_evb_arm/board.h @@ -42,7 +42,7 @@ /* Optional feature - used by nuvoton */ #define NPCX_UART_MODULE2 0 /* 0:GPIO10/11 1:GPIO64/65 as UART */ #define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/ -#define NPCX_TACH_SEL2 0 /* 0:GPIO40/A4 1:GPIO93/D3 as TACH */ +#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */ /* Enable SHI PU on transition to S0. Disable the PU otherwise for leakage. */ #define NPCX_SHI_CS_PU /* Enable bypass since shi outputs invalid data when across 256B boundary */ |