diff options
| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2015-09-05 17:27:37 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2015-09-16 14:49:32 -0700 |
| commit | 558c465165acf494905fa59c822c7190b4646899 (patch) | |
| tree | a20a512da9d8aed29cb46d99b8df0b8bb0ab5714 /board/npcx_evb_arm | |
| parent | d58e54730c03290296df5bb65cb84264e4b2facc (diff) | |
| download | chrome-ec-558c465165acf494905fa59c822c7190b4646899.tar.gz | |
cleanup: Remove CDRAM / CODERAM CONFIGs
CDRAM / CODERAM configs were previously used for chips which copied code
from external SPI to program memory prior to execution, and were used
inconsistently between npcx and mec1322.
These CONFIGs are now completely redundant given new configs like
CONFIG_MAPPED_STORAGE_BASE and CONFIG_EXTERNAL_STORAGE.
BRANCH=None
BUG=chrome-os-partner:23796
TEST=With entire patch series, on both Samus and Glados:
- Verify 'version' EC console command is correct
- Verify 'flashrom -p ec -r read.bin' reads back EC image
- Verify software sync correctly flashes both EC and PD RW images
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I0e054ab4c939f9dcf54abee8e5ebd9b2e42fe9c4
Reviewed-on: https://chromium-review.googlesource.com/297804
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'board/npcx_evb_arm')
| -rw-r--r-- | board/npcx_evb_arm/board.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/board/npcx_evb_arm/board.h b/board/npcx_evb_arm/board.h index 4c795059ac..e9ccaea25b 100644 --- a/board/npcx_evb_arm/board.h +++ b/board/npcx_evb_arm/board.h @@ -8,9 +8,6 @@ #ifndef __CROS_EC_BOARD_H #define __CROS_EC_BOARD_H -/* Support Code RAM architecture (Run code in RAM) */ -#define CONFIG_CODERAM_ARCH - /* Optional modules */ #define CONFIG_ADC #define CONFIG_PWM |