diff options
| author | Mulin Chao <mlchao@nuvoton.com> | 2016-04-29 13:35:54 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-05-06 18:58:20 -0700 |
| commit | 3391ef950a0ba7daf069fb760daadb872ca71cfe (patch) | |
| tree | 1580a7acf7993076fdd408a8c56b87c7e865f983 /board/npcx_evb_arm | |
| parent | b13f300ca3a322a3d20d1f27270924d50113b643 (diff) | |
| download | chrome-ec-3391ef950a0ba7daf069fb760daadb872ca71cfe.tar.gz | |
npcx: shi: Improve reliability of SPI host command interface
- Fix output buffer filling races
- Limit response size to 256 bytes to work-around forced low bit on
257th byte
- Modify CS glitch to handle CS-to-clock delay
- Make CS GPIO interrupt pri 0 to ensure SHI interrupts aren't serviced
first
TEST=`while true; do ectool version; done > /usr/local/log` on kevin,
verify failure occurs about every ~72000 commands (~360000 host commands)
BRANCH=None
BUG=chrome-os-partner:52372
Change-Id: I5c3d90bf510ed782973b57c2b7497441434c1708
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/341492
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'board/npcx_evb_arm')
| -rw-r--r-- | board/npcx_evb_arm/board.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/board/npcx_evb_arm/board.h b/board/npcx_evb_arm/board.h index ca572b8a0b..bc0e748bdd 100644 --- a/board/npcx_evb_arm/board.h +++ b/board/npcx_evb_arm/board.h @@ -42,6 +42,10 @@ #define NPCX_UART_MODULE2 0 /* 0:GPIO10/11 1:GPIO64/65 as UART */ #define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/ #define NPCX_TACH_SEL2 0 /* 0:GPIO40/A4 1:GPIO93/D3 as TACH */ +/* Enable SHI PU on transition to S0. Disable the PU otherwise for leakage. */ +#define NPCX_SHI_CS_PU +/* Enable bypass since shi outputs invalid data when across 256B boundary */ +#define NPCX_SHI_BYPASS_OVER_256B /* Optional for testing */ #undef CONFIG_PECI |