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| author | Koro Chen <koro.chen@mediatek.com> | 2016-03-16 14:44:18 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-03-16 06:43:24 -0700 |
| commit | 74d2e46ea3d3a1c52cfd3802454c016e5812d7e7 (patch) | |
| tree | 224be02e8697eb12031752e03221227df9209765 /board/oak/board.h | |
| parent | c1fbaa22c62c621e414dd0b58e90ad972b4ddb44 (diff) | |
| download | chrome-ec-74d2e46ea3d3a1c52cfd3802454c016e5812d7e7.tar.gz | |
oak: Clean up CONFIG_PMIC_FW_LONG_PRESS_TIMER related codes
CONFIG_PMIC_FW_LONG_PRESS_TIMER was ported long time ago from
Tegra, but the codes are actually not used and erroneous.
It might wrongly trigger set_pmic_pwron(0), and turn off
PMIC power accidentally. This causes POWER_GOOD lost and
power state will go back to S5 during boot up.
Clean up the codes by referencing check_for_power_off_event()
of Rockchip.
BRANCH=none
BUG=none
TEST=bootup and press power button quickly right after we are in S0.
Bootup should still complete normally.
Change-Id: Ie034efa3575dbebae4debb1afc206fddd9116350
Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/332724
Reviewed-by: Rong Chang <rongchang@chromium.org>
Diffstat (limited to 'board/oak/board.h')
| -rw-r--r-- | board/oak/board.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/board/oak/board.h b/board/oak/board.h index 5d6bea437e..82ee7291ac 100644 --- a/board/oak/board.h +++ b/board/oak/board.h @@ -83,7 +83,6 @@ #define CONFIG_LID_SWITCH #define CONFIG_LOW_POWER_IDLE #define CONFIG_MKBP_EVENT -#define CONFIG_PMIC_FW_LONG_PRESS_TIMER #define CONFIG_POWER_BUTTON #define CONFIG_POWER_COMMON #define CONFIG_USB_CHARGER |