diff options
| author | Rong Chang <rongchang@chromium.org> | 2015-06-11 20:38:21 +0800 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-06-17 20:24:18 +0000 |
| commit | dd1987051b473e74dab3490921d0cc77c76fcac3 (patch) | |
| tree | 0e4f28d2302d3dfc33b67082139ef814068a43c3 /board/oak/gpio.inc | |
| parent | 4982391dc27960c5af4e1814d627154a8aac3e29 (diff) | |
| download | chrome-ec-dd1987051b473e74dab3490921d0cc77c76fcac3.tar.gz | |
oak: enable USBC superspeed mux
This change enables USB3/DP superspeed mux. Oak's two type-C ports share
one DP hardware. When both ports connect to DP output device, only the
first DP signal will be routed to SoC. On exit dp mode, oak sends HPD
again if the other port's DP flag is on.
BRANCH=none
BUG=chrome-os-partner:41404
TEST=none
Change-Id: I7eebc0b2354f93d7421bf83796294a6b2acf4c3b
Signed-off-by: Rong Chang <rongchang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/277000
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Diffstat (limited to 'board/oak/gpio.inc')
| -rw-r--r-- | board/oak/gpio.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/oak/gpio.inc b/board/oak/gpio.inc index 701e9c84cb..9b64561ec8 100644 --- a/board/oak/gpio.inc +++ b/board/oak/gpio.inc @@ -73,7 +73,7 @@ GPIO(USB_C1_5V_OUT, PIN(D, 10), GPIO_OUT_LOW) /* USBC port 1 5V */ GPIO(USB_C1_CHARGE_L, PIN(D, 11), GPIO_OUT_LOW) /* USBC port 1 charge */ GPIO(USB_PD_VBUS_WAKE, PIN(B, 15), GPIO_OUT_LOW) /* PD VBUS wake */ GPIO(USB_DP_HPD, PIN(F, 3), GPIO_OUT_LOW) -GPIO(DP_MUX_ENABLE, PIN(E, 6), GPIO_OUT_HIGH) +GPIO(DP_MUX_EN_L, PIN(E, 6), GPIO_OUT_LOW) GPIO(DP_SWITCH_CTL, PIN(E, 5), GPIO_OUT_LOW) #ifdef CONFIG_BOARD_OAK_REV_1 |