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| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2019-10-02 14:27:47 -0600 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-11-01 18:43:42 +0000 |
| commit | 9577704f30c7e824c0590264df22d95a2c706575 (patch) | |
| tree | 566b5beeeae8b343803718101ba0b00c940506cb /board/pdeval-stm32f072/PD_evaluation.md | |
| parent | e8121e83e478fef2d5a29304be900311f3f020c4 (diff) | |
| download | chrome-ec-9577704f30c7e824c0590264df22d95a2c706575.tar.gz | |
Rename CONFIG_USB_PD_PORT_COUNT as CONFIG_USB_PD_PORT_MAX_COUNT
Certain SKUs of certain boards have lesser number of USB PD ports than
defined by CONFIG_USB_PD_PORT_COUNT. Hence rename
CONFIG_USB_PD_PORT_COUNT as CONFIG_USB_PD_PORT_MAX_COUNT.
BUG=b:140816510, b:143196487
BRANCH=octopus
TEST=make -j buildall; Boot to ChromeOS
Change-Id: I7c33b27150730a1a3b5813b7b4a72fd24ab73c6a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1879337
Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'board/pdeval-stm32f072/PD_evaluation.md')
| -rw-r--r-- | board/pdeval-stm32f072/PD_evaluation.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/pdeval-stm32f072/PD_evaluation.md b/board/pdeval-stm32f072/PD_evaluation.md index 395466f477..95e31996fc 100644 --- a/board/pdeval-stm32f072/PD_evaluation.md +++ b/board/pdeval-stm32f072/PD_evaluation.md @@ -35,7 +35,7 @@ then document the new `CONFIG_USB_PD_TCPM_` variable in the [include/config.h](. ### Board configuration -In [board/pdeval-stm32f072/board.h](board.h), you can update `CONFIG_USB_PD_PORT_COUNT` to the actual number of ports on your board. +In [board/pdeval-stm32f072/board.h](board.h), you can update `CONFIG_USB_PD_PORT_MAX_COUNT` to the actual number of ports on your board. You also need to create/delete the corresponding `PD_Cx` tasks in [board/pdeval-stm32f072/ec.tasklist](ec.tasklist). By default, the firmware is using I2C1 with SCL/SDA on pins PB6 and PB7, running with a 100kHz clock, and tries to talk to TCPCs at i2c slave addresses 0x9c and 0x9e. |