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authorPaul Ma <magf@bitland.corp-partner.google.com>2018-06-19 15:18:27 +0800
committerchrome-bot <chrome-bot@chromium.org>2018-06-21 12:18:08 -0700
commit5087723490bcad60a4e833e106170e861bd1a159 (patch)
tree4ae2f993e166d531fa6e85fa0c92e85372e06974 /board/phaser/gpio.inc
parent698d62e1220aef10b8a6bef866ebe4bb3bef699d (diff)
downloadchrome-ec-5087723490bcad60a4e833e106170e861bd1a159.tar.gz
phaser: enable phaser motion sensor drivers
This patch add phaser base and lid accel sensor support. Lid sensor type is lis2de, it has the same register interface as lis2dh, so they share the same driver. Since it has a very small fifo, use it in forced mode. Signed-off-by: Paul Ma <magf@bitland.corp-partner.google.com> BRANCH=none BUG=b:110013316 TEST=boot phaser board, base and lid sensor can be inititalized successfully. use console command "accelinfo on", both sensors has valid output. Change-Id: Ie8514ea449fec41c6b1e0b6be1f2ae88458d119c Reviewed-on: https://chromium-review.googlesource.com/1105688 Commit-Ready: Jett Rink <jettrink@chromium.org> Tested-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'board/phaser/gpio.inc')
-rw-r--r--board/phaser/gpio.inc7
1 files changed, 3 insertions, 4 deletions
diff --git a/board/phaser/gpio.inc b/board/phaser/gpio.inc
index b44e15c34e..6580256649 100644
--- a/board/phaser/gpio.inc
+++ b/board/phaser/gpio.inc
@@ -34,13 +34,12 @@ GPIO_INT(ALL_SYS_PGOOD, PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt) /* PM
/* Other interrupts */
GPIO_INT(WP_L, PIN(A, 1), GPIO_INT_BOTH, switch_interrupt) /* EC_WP_ODL */
+GPIO_INT(BASE_SIXAXIS_INT_L, PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, lsm6dsm_interrupt)
+GPIO(LID_ACCEL_INT_L, PIN(5, 0), GPIO_INPUT | GPIO_SEL_1P8V)
+
/* TODO: Convert to GPIO_INT with tablet_mode_isr */
GPIO(TABLET_MODE_L, PIN(8, 6), GPIO_INPUT)
-/* TODO(b/74932344): Make it as an interrupt after driver supports this */
-GPIO(BASE_SIXAXIS_INT_L, PIN(5, 6), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(LID_ACCEL_INT_L, PIN(5, 0), GPIO_INPUT | GPIO_SEL_1P8V)
-
/* Define PCH_SLP_S0_L after all interrupts if CONFIG_POWER_S0IX not defined. */
#ifndef CONFIG_POWER_S0IX
GPIO(PCH_SLP_S0_L, PIN(A, 4), GPIO_INPUT) /* SLP_S0_L */