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authorJett Rink <jettrink@chromium.org>2019-10-18 11:57:13 -0600
committerCommit Bot <commit-bot@chromium.org>2019-10-19 20:17:16 +0000
commit58ac5f86059f85e24036fd4933a024dadae28f25 (patch)
tree51e75943e0809fde33894b26e695be1b7527769b /board/phaser
parent6e785cd95b5070e329785daf7166bb8823dcf48d (diff)
downloadchrome-ec-58ac5f86059f85e24036fd4933a024dadae28f25.tar.gz
octopus: lock gpio config for reset signal
BRANCH=octopus BUG=b:142953493 TEST=verify that later modification of gpio flag will no allow driving signal high. Change-Id: I0b8c1503ba8c03afa3eb6fa4f921b3480106f05b Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1869407 Commit-Queue: Edward Hill <ecgh@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
Diffstat (limited to 'board/phaser')
-rw-r--r--board/phaser/gpio.inc7
1 files changed, 6 insertions, 1 deletions
diff --git a/board/phaser/gpio.inc b/board/phaser/gpio.inc
index c70d0a543e..a47a816675 100644
--- a/board/phaser/gpio.inc
+++ b/board/phaser/gpio.inc
@@ -88,8 +88,13 @@ GPIO(EC_BATT_PRES_L, PIN(E, 5), GPIO_INPUT)
* being asserted. Also, it should be fine to have the EC in hibernate when H1
* or servo wants to hold the EC in reset since VCC1 will be down and so entire
* EC logic (except PSL) as well as AP will be in reset.
+ *
+ * We need to lock the setting so this gpio can't be reconfigured to overdrive
+ * the real reset signal. (This is the PSL input pin not the real reset pin).
*/
-GPIO(EC_RST_ODL, PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH)
+GPIO(EC_RST_ODL, PIN(0, 2), GPIO_INT_BOTH |
+ GPIO_HIB_WAKE_HIGH |
+ GPIO_LOCKED)
/*
* PCH_PROCHOT_ODL is primarily for monitoring the PROCHOT# signal which is