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| author | Randall Spangler <rspangler@chromium.org> | 2013-05-14 14:16:44 -0700 |
|---|---|---|
| committer | ChromeBot <chrome-bot@google.com> | 2013-05-16 13:07:15 -0700 |
| commit | 3c2c1398ec993cc597903a4d4ba38546182b7053 (patch) | |
| tree | 0a3055616a45d7a42ae5bca4292a5aa4eb23a1a2 /board/pit | |
| parent | 23ece32e08cb188c36eb3162b7519b4713275d6b (diff) | |
| download | chrome-ec-3c2c1398ec993cc597903a4d4ba38546182b7053.tar.gz | |
Set SPI lines to inputs when AP is off
When AP is off, turn off pullup on NSS, and set MISO to an input so
the SPI module won't drive it high if the last sent bit was a 1. This
reduces leakage when the AP is off.
This patch also fixes a bug where gpio_set_alternate_function() set
the wrong pins to normal-mode when func=-1; that didn't hit anything
else because that functionality wasn't used on STM32 until now.
BUG=chrome-os-partner:19304
BRANCH=none
TEST=boot pit
On EC console, with AP on, 'rw 0x40020000' returns
read 0x40020000 = 0x6569aa20 <- must have 0x____aa__
Then 'apshutdown' and 'rw 0x40020000' returns
read 0x40020000 = 0x65690020 <- must have 0x____00__
The 'power on' and AP turns back on. At u-boot prompt,
'sspi 2:0 256 9f00000000' returns
FDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFEEC010001
(some number of 0xFD's followed by FEEC...) This shows SPI
functionality is restored when AP is powered back on, and not
just at init time.
Change-Id: Ia3cd3e0bc222dc663d635509918fa3d383fd7971
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/51182
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'board/pit')
| -rw-r--r-- | board/pit/board.c | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/board/pit/board.c b/board/pit/board.c index e4b8eef624..7bd796f207 100644 --- a/board/pit/board.c +++ b/board/pit/board.c @@ -97,13 +97,6 @@ void board_config_post_gpio_init(void) /* TIM2_CH2 on PB3 */ gpio_set_alternate_function(GPIO_B, (1 << 3), GPIO_ALT_TIM2); - - /* SPI1 on pins PA4-7 */ - gpio_set_alternate_function(GPIO_A, - (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7), - GPIO_ALT_SPI); - /* 40 MHz pin speed */ - STM32_GPIO_OSPEEDR(GPIO_A) |= 0xff00; } #ifdef CONFIG_PMU_BOARD_INIT |