diff options
author | Todd Broch <tbroch@chromium.org> | 2015-04-16 16:17:39 -0700 |
---|---|---|
committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-05-01 01:08:05 +0000 |
commit | 56653dec06ede2c62ec35c74f0e133f18dd7ea50 (patch) | |
tree | 9f08173d421c853341867a2a38621eeec5525de9 /board/plankton | |
parent | 8d62b79841f59f30da3a85aece4bbc88bcc9e7cd (diff) | |
download | chrome-ec-56653dec06ede2c62ec35c74f0e133f18dd7ea50.tar.gz |
plankton: Reset re-driver on boot and configure training more.
Commit, '0016de8 - plankton: Initialize re-driver', didn't account for
the state of the redriver at the time it was being initialized in
manual training mode. This led to inconsitencies of manual training
configuration.
This CL resets the SN75DP130 via software to guarantee configuration
regardless of cold versus warm boot.
Additionally I learned that manual training requires setting of both
the link_bw_set (5.4gbps) and lane_count_set (4) in order make the
back side of the redriver happy. This can ONLY be done however in the
presence of HPD high. Future CL will incorporate this DPCD init into
HDP interrupt handler as well.
Signed-off-by: Todd Broch <tbroch@chromium.org>
BRANCH=none
BUG=chrome-os-partner:35153
TEST=manual,
samus + plankton successfully drives Samsung U28D590 from cold or warm
boot of either plankton or samus in both polarities. Note DisplayPort
cable must be connected to external monitor prior to power on or reset.
macbook (2015 type-C) + plankton also works.
Change-Id: I8b34341d10f64abfa55c18f70c842a4446f36fa8
Reviewed-on: https://chromium-review.googlesource.com/266526
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Todd Broch <tbroch@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
Diffstat (limited to 'board/plankton')
-rw-r--r-- | board/plankton/board.c | 78 |
1 files changed, 68 insertions, 10 deletions
diff --git a/board/plankton/board.c b/board/plankton/board.c index ebdd85f722..7140942ab1 100644 --- a/board/plankton/board.c +++ b/board/plankton/board.c @@ -165,26 +165,84 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); /* 8-bit address */ #define SN75DP130_I2C_ADDR 0x5c +/* + * Pin number for active-high reset from PCA9534 to CMOS pull-down to + * SN75DP130's RSTN (active-low) + */ +#define REDRIVER_RST_PIN 0x1 -static void sn75dp130_redriver_init(void) +static int sn75dp130_i2c_write(uint8_t index, uint8_t value) { - int i; + return i2c_write8(I2C_PORT_MASTER, SN75DP130_I2C_ADDR, index, value); +} - /* Disable squelch detect */ - i2c_write8(1, SN75DP130_I2C_ADDR, 0x3, 0x1a); - /* Disable link training on re-driver source side */ - i2c_write8(1, SN75DP130_I2C_ADDR, 0x4, 0x0); +/** + * Reset redriver. + * + * Note, MUST set SW15 to 'PD' in order to control i2c from PD-MCU. This can + * NOT be done via software. + */ +static int sn75dp130_reset(void) +{ + int rv; + + rv = pca9534_config_pin(I2C_PORT_MASTER, 0x40, REDRIVER_RST_PIN, + PCA9534_OUTPUT); + /* Assert (its active high) */ + rv |= pca9534_set_level(I2C_PORT_MASTER, 0x40, REDRIVER_RST_PIN, 1); + /* datasheet recommends > 100usec */ + usleep(200); + + /* De-assert */ + rv |= pca9534_set_level(I2C_PORT_MASTER, 0x40, REDRIVER_RST_PIN, 0); + /* datasheet recommends > 400msec */ + usleep(450 * MSEC); + return rv; +} + +static int sn75dp130_dpcd_init(void) +{ + int i, rv; + + /* set upper & middle DPCD addr ... constant for writes below */ + rv = sn75dp130_i2c_write(0x1c, 0x0); + rv |= sn75dp130_i2c_write(0x1d, 0x1); + + /* link_bw_set: 5.4gbps */ + rv |= sn75dp130_i2c_write(0x1e, 0x0); + rv |= sn75dp130_i2c_write(0x1f, 0x14); + + /* lane_count_set: 4 */ + rv |= sn75dp130_i2c_write(0x1e, 0x1); + rv |= sn75dp130_i2c_write(0x1f, 0x4); /* * Force Link voltage level & pre-emphasis by writing each of the lane's * DPCD config registers 103-106h accordingly. */ - i2c_write8(1, SN75DP130_I2C_ADDR, 0x1c, 0x0); - i2c_write8(1, SN75DP130_I2C_ADDR, 0x1d, 0x1); for (i = 0x3; i < 0x7; i++) { - i2c_write8(1, SN75DP130_I2C_ADDR, 0x1e, i); - i2c_write8(1, SN75DP130_I2C_ADDR, 0x1f, 0x3); + rv |= sn75dp130_i2c_write(0x1e, i); + rv |= sn75dp130_i2c_write(0x1f, 0x3); } + return rv; +} + +static int sn75dp130_redriver_init(void) +{ + int rv; + + rv = sn75dp130_reset(); + + /* Disable squelch detect */ + rv |= sn75dp130_i2c_write(0x3, 0x1a); + /* Disable link training on re-driver source side */ + rv |= sn75dp130_i2c_write(0x4, 0x0); + + /* Can only configure DPCD portion of redriver in presence of an HPD */ + if (gpio_get_level(GPIO_DPSRC_HPD)) + sn75dp130_dpcd_init(); + + return rv; } static void board_init(void) |