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authorFurquan Shaikh <furquan@chromium.org>2017-11-13 12:03:29 -0800
committerchrome-bot <chrome-bot@chromium.org>2017-11-14 10:11:18 -0800
commit7f46978b5b70065c2129237e3908936cf67b82c0 (patch)
treed0f8cb460ecaa9335791c4f88cef2c7038ae4898 /board/poppy/gpio.inc
parent54588e40a7bd2b94a5fe96c2eecd435bdc4db110 (diff)
downloadchrome-ec-7f46978b5b70065c2129237e3908936cf67b82c0.tar.gz
poppy/soraka: Change USB_C1_PD_RST_L to be GPIO_ODR_HIGH
Reference CL: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/762066 The reset line for the parade TCPC on port 1, has an external 1k pull up resistor. However, the gpio.inc description for this line was set to OUT_LOW which results in a short reset pulse. This can lead to an external charger seeing an unattach event and dropping VBUS. On Soraka systems with certain chargers this results in a continuous reboot loop when no battery is connected. Changing the default state of this line to ODR_HIGH prevents reset from being pulled low until the EC is intializing the TCPC and fixes the continous reboot loop issue when no battery is connected. BUG=b:69198785 BRANCH=None TEST=On a Soraka system, verified that connecting Lenovo Type C charger on Parade port did not result in reboot loop when no battery is connected. Earlier this same setup resulted in continuous reboot loop. Change-Id: I5138e129431ee4f0c1c6ceaaac5ab288c3ab6233 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/767070 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'board/poppy/gpio.inc')
-rw-r--r--board/poppy/gpio.inc2
1 files changed, 1 insertions, 1 deletions
diff --git a/board/poppy/gpio.inc b/board/poppy/gpio.inc
index e4b1d53165..9c12a1db2c 100644
--- a/board/poppy/gpio.inc
+++ b/board/poppy/gpio.inc
@@ -107,7 +107,7 @@ GPIO(USB_C1_5V_EN, PIN(B, 1), GPIO_OUT_LOW) /* C1 5V Enable */
GPIO(USB_C1_3A_EN, PIN(3, 5), GPIO_OUT_LOW) /* C1 3A Enable */
GPIO(USB_C1_CHARGE_L, PIN(C, 3), GPIO_OUT_LOW) /* C1 Charge enable */
GPIO(USB_C0_PD_RST_L, PIN(0, 3), GPIO_OUT_LOW) /* C0 PD Reset */
-GPIO(USB_C1_PD_RST_L, PIN(7, 4), GPIO_OUT_LOW) /* C1 PD Reset */
+GPIO(USB_C1_PD_RST_L, PIN(7, 4), GPIO_ODR_HIGH) /* C1 PD Reset */
GPIO(USB_C0_DP_HPD, PIN(9, 4), GPIO_INPUT) /* C0 DP Hotplug Detect */
GPIO(USB_C1_DP_HPD, PIN(A, 5), GPIO_INPUT) /* C1 DP Hotplug Detect */
GPIO(USB_C0_TCPC_PWR, PIN(8, 4), GPIO_OUT_LOW) /* Enable C0 TCPC Power */