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| author | Peter Marheine <pmarheine@chromium.org> | 2019-11-20 13:03:58 +1100 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-12-10 06:39:43 +0000 |
| commit | 33cc661bd206d8f5a3d599c5cde503a3f89f6b2e (patch) | |
| tree | 050fa67612c7f14a1ff70a8fa9899b96ff49afb9 /board/puff/board.h | |
| parent | 0ee58e53ecb9417b7c264be0d3c199e1919fafd6 (diff) | |
| download | chrome-ec-33cc661bd206d8f5a3d599c5cde503a3f89f6b2e.tar.gz | |
power/cometlake-discrete: implement power sequencingstabilize-12748.B-master
A first go at the power sequencing needed for Puff. This abuses the
Intel common power code a little bit because we don't actually have all
the inputs it assumes, but that seems preferable to replacing it
wholesale.
The one limitation right now is inability to detect transitions on the
rails that we only have analog monitoring on; either we need to design
a way to monitor those, or decide that detecting dropouts on those rails
is unimportant.
BUG=b:143188569
TEST=still builds
BRANCH=None
Change-Id: Ia960f5dd2ccfb1ca2c7d4107ba4e3737adc8f69f
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1925787
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Diffstat (limited to 'board/puff/board.h')
| -rw-r--r-- | board/puff/board.h | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/board/puff/board.h b/board/puff/board.h index 85337b55af..0c4dcd2b2b 100644 --- a/board/puff/board.h +++ b/board/puff/board.h @@ -66,7 +66,6 @@ #define CONFIG_CHIPSET_COMETLAKE_DISCRETE /* check */ #define CONFIG_CHIPSET_CAN_THROTTLE -#define CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK #define CONFIG_CHIPSET_RESET_HOOK #define CONFIG_CPU_PROCHOT_ACTIVE_LOW @@ -231,10 +230,12 @@ void led_critical(void); #define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L #define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L #define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L -/* No equivalent signals for these pins, need to refactor the power handling */ -#define GPIO_RSMRST_L_PGOOD GPIO_PG_VPRIM_CORE_A_OD -#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_PG_VPRIM_CORE_A_OD -#define GPIO_EN_A_RAILS GPIO_EN_ROA_RAILS #define GPIO_AC_PRESENT GPIO_BJ_ADP_PRESENT_L +/* + * There is no RSMRST input, so alias it to the output. This short-circuits + * common_intel_x86_handle_rsmrst. + */ +#define GPIO_RSMRST_L_PGOOD GPIO_PCH_RSMRST_L + #endif /* __CROS_EC_BOARD_H */ |