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| author | Peter Marheine <pmarheine@chromium.org> | 2020-05-11 11:49:38 +1000 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-05-19 08:46:37 +0000 |
| commit | 6ce2d3106156c2ea3e51b8a088fd6b66a2397eb9 (patch) | |
| tree | d3789d0ad187b546febc8121f9281fd225959c1e /board/puff | |
| parent | 5e32f948d370fff182616bd987ffdc794f6858a6 (diff) | |
| download | chrome-ec-6ce2d3106156c2ea3e51b8a088fd6b66a2397eb9.tar.gz | |
cortex-m: provide a function to set IRQ priority
On Puff we need to increase some IRQ priorities to meet strict timing
requirements. To support that, provide a function encapsulating the bit
manipulations to adjust the priority of a single IRQ and update task.c
to take advantage of it.
BUG=None
BRANCH=None
TEST=Still builds.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Change-Id: I9534f5733db48b9650a55f30e5209918a5eb24b1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2192456
Reviewed-by: Andrew McRae <amcrae@chromium.org>
Diffstat (limited to 'board/puff')
| -rw-r--r-- | board/puff/board.c | 14 |
1 files changed, 2 insertions, 12 deletions
diff --git a/board/puff/board.c b/board/puff/board.c index f28d64615f..187de62cc8 100644 --- a/board/puff/board.c +++ b/board/puff/board.c @@ -394,16 +394,6 @@ const struct ina3221_t ina3221[] = { }; const unsigned int ina3221_count = ARRAY_SIZE(ina3221); -static void override_interrupt_priority(int irq, int priority) -{ - const uint32_t prio_shift = irq % 4 * 8 + 5; - - CPU_NVIC_PRI(irq / 4) = - (CPU_NVIC_PRI(irq / 4) & - ~(0x7 << prio_shift)) | - (priority << prio_shift); -} - static void board_init(void) { uint8_t *memmap_batt_flags; @@ -419,12 +409,12 @@ static void board_init(void) * requiring faster response must be higher priority. */ /* CPU_C10_GATE_L on GPIO6.7: must be ~instant for ~60us response. */ - override_interrupt_priority(NPCX_IRQ_WKINTH_1, 1); + cpu_set_interrupt_priority(NPCX_IRQ_WKINTH_1, 1); /* * slp_s3_interrupt (GPIOA.5 on WKINTC_0) must respond within 200us * (tPLT18); less critical than the C10 gate. */ - override_interrupt_priority(NPCX_IRQ_WKINTC_0, 2); + cpu_set_interrupt_priority(NPCX_IRQ_WKINTC_0, 2); update_port_limits(); gpio_enable_interrupt(GPIO_BJ_ADP_PRESENT_L); |