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| author | Randall Spangler <rspangler@chromium.org> | 2013-10-10 13:49:39 -0700 |
|---|---|---|
| committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2013-10-11 03:58:09 +0000 |
| commit | 1006187c61bee2a9700781e7a6fcd23b3cfad89b (patch) | |
| tree | 4a7f307cc1cf073933e982c8039ca87d83e7ab47 /board/rambi/board.c | |
| parent | a1191b92d2f5784e2f4e1c5f40d4af1a41e55fda (diff) | |
| download | chrome-ec-1006187c61bee2a9700781e7a6fcd23b3cfad89b.tar.gz | |
Add baytrail power sequencing
This is an initial version of power sequencing for the rambi rev.1
boards. It has a workaround for a rev.1 board problem; this requires
turning on PP5000 early.
BUG=chrome-os-partner:22895
BRANCH=none
TEST=AP should power on to S0 (PLTRST# deasserts) automatically when EC boots
Then 'apshutdown' should drag it back to G3.
Then 'powerbtn' should take it back to S0.
Change-Id: Id9bc6fe9b55fce3eb46ce1265891724ec7a4ae20
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172675
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'board/rambi/board.c')
| -rw-r--r-- | board/rambi/board.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/rambi/board.c b/board/rambi/board.c index 38f4262fe4..72be16f3c0 100644 --- a/board/rambi/board.c +++ b/board/rambi/board.c @@ -77,7 +77,7 @@ const struct gpio_info gpio_list[] = { {"LPC_CLKRUN_L", LM4_GPIO_M, (1<<2), GPIO_ODR_HIGH, NULL}, {"PCH_CORE_PWROK", LM4_GPIO_F, (1<<5), GPIO_OUT_LOW, NULL}, {"PCH_PWRBTN_L", LM4_GPIO_H, (1<<0), GPIO_ODR_HIGH, NULL}, - {"PCH_RCIN_L", LM4_GPIO_F, (1<<3), GPIO_ODR_LOW, NULL}, + {"PCH_RCIN_L", LM4_GPIO_F, (1<<3), GPIO_ODR_HIGH, NULL}, {"PCH_RSMRST_L", LM4_GPIO_F, (1<<1), GPIO_OUT_LOW, NULL}, {"PCH_SMI_L", LM4_GPIO_F, (1<<4), GPIO_ODR_HIGH, NULL}, {"PCH_SOC_OVERRIDE_L", LM4_GPIO_G, (1<<1), GPIO_OUT_HIGH, NULL}, |