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| author | Randall Spangler <rspangler@chromium.org> | 2013-10-10 13:49:39 -0700 |
|---|---|---|
| committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2013-10-11 03:58:09 +0000 |
| commit | 1006187c61bee2a9700781e7a6fcd23b3cfad89b (patch) | |
| tree | 4a7f307cc1cf073933e982c8039ca87d83e7ab47 /board/rambi/board.h | |
| parent | a1191b92d2f5784e2f4e1c5f40d4af1a41e55fda (diff) | |
| download | chrome-ec-1006187c61bee2a9700781e7a6fcd23b3cfad89b.tar.gz | |
Add baytrail power sequencing
This is an initial version of power sequencing for the rambi rev.1
boards. It has a workaround for a rev.1 board problem; this requires
turning on PP5000 early.
BUG=chrome-os-partner:22895
BRANCH=none
TEST=AP should power on to S0 (PLTRST# deasserts) automatically when EC boots
Then 'apshutdown' should drag it back to G3.
Then 'powerbtn' should take it back to S0.
Change-Id: Id9bc6fe9b55fce3eb46ce1265891724ec7a4ae20
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172675
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'board/rambi/board.h')
| -rw-r--r-- | board/rambi/board.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/board/rambi/board.h b/board/rambi/board.h index deb00abc15..2cc95f1fb1 100644 --- a/board/rambi/board.h +++ b/board/rambi/board.h @@ -11,6 +11,9 @@ /* Optional features */ #define CONFIG_BACKLIGHT_LID #define CONFIG_BOARD_VERSION +#define CONFIG_CHIPSET_BAYTRAIL +#define CONFIG_CHIPSET_CAN_THROTTLE +#define CONFIG_CHIPSET_X86 #define CONFIG_CMD_GSV #define CONFIG_EXTPOWER_GPIO #define CONFIG_KEYBOARD_COL2_INVERTED @@ -35,9 +38,6 @@ #define CONFIG_CHARGER_INPUT_CURRENT 4032 /* mA, about half max */ #define CONFIG_CHARGER_SENSE_RESISTOR 10 /* Charge sense resistor, mOhm */ #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 /* Input sensor resistor, mOhm */ -#define CONFIG_CHIPSET_CAN_THROTTLE -#define CONFIG_CHIPSET_HASWELL -#define CONFIG_CHIPSET_X86 #define CONFIG_USB_PORT_POWER_DUMB #endif @@ -107,7 +107,7 @@ enum gpio_signal { GPIO_LPC_CLKRUN_L, /* Request that PCH drive LPC clock */ GPIO_PCH_CORE_PWROK, /* Indicate core well power is stable */ GPIO_PCH_PWRBTN_L, /* Power button output to PCH */ - GPIO_PCH_RCIN_L, /* RCIN# line to PCH (for 8042 emulation) */ + GPIO_PCH_RCIN_L, /* Reset line to PCH (for 8042 emulation) */ GPIO_PCH_RSMRST_L, /* Reset PCH resume power plane logic */ GPIO_PCH_SMI_L, /* System management interrupt to PCH */ GPIO_PCH_SOC_OVERRIDE_L, /* SOC override signal to PCH; when high, ME |