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| author | Nicolas Boichat <drinkcat@chromium.org> | 2018-03-19 10:12:32 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-05-16 05:08:30 -0700 |
| commit | 9be407f10ed2710a4a29a94ef96f6a6c97a2f2a1 (patch) | |
| tree | 0d1cf542bbb6ade6fa23d961615136826e2c05e3 /board/reef | |
| parent | f139d3a0ca9215b5b5bb2abc1f120ff6171036c9 (diff) | |
| download | chrome-ec-9be407f10ed2710a4a29a94ef96f6a6c97a2f2a1.tar.gz | |
chip/npcx: Increase default stack size for tasks
Usually, we enable CONFIG_FPU on NPCX, which requires larger
stack size. Also, NPCX has very deep call patch in I2C transactions
(in particular, I2C recovery path), so it generally requires larger
stack.
To make the code fit, however, we need to reduce the accelerometer
fifo depth from 1024 to 512, on a few boards.
BRANCH=none
BUG=b:75234824
TEST=make buildall -j, stackanalyzer result on poppy looks a little
better.
Change-Id: I37b5a2a97a760dc4fd225253c23962d74e25605a
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/967963
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'board/reef')
| -rw-r--r-- | board/reef/board.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/reef/board.h b/board/reef/board.h index a3060be05f..a1b45ddf08 100644 --- a/board/reef/board.h +++ b/board/reef/board.h @@ -205,7 +205,7 @@ #define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL /* FIFO size is in power of 2. */ -#define CONFIG_ACCEL_FIFO 1024 +#define CONFIG_ACCEL_FIFO 512 /* Depends on how fast the AP boots and typical ODRs */ #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO / 3) |