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authorAaron Durbin <adurbin@chromium.org>2016-05-24 08:49:27 -0500
committerchrome-bot <chrome-bot@chromium.org>2016-05-24 15:46:02 -0700
commitc8a49484176144dfd5d99969a74af3aba27a8e5a (patch)
tree5da81a895f4c7a353f3d55fb9472ed79b08ce541 /board/reef
parent58b9c3ef174d8e384bbb9f1f88c86eb6c3477648 (diff)
downloadchrome-ec-c8a49484176144dfd5d99969a74af3aba27a8e5a.tar.gz
reef: change USB_C0_PD_INT voltage tolerance
The USB_C0_PD_INT signal is actually at 3.3V levels. Don't mark the voltage sensitivity to 1.8V. BUG=chrome-os-partner:53035 BRANCH=None TEST=Rachel ran with resulting image. Nothing bad observed. Change-Id: I36bc3f911b715dc967cc8f23dfc70c3d0e5023d2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/346734 Reviewed-by: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'board/reef')
-rw-r--r--board/reef/gpio.inc2
1 files changed, 1 insertions, 1 deletions
diff --git a/board/reef/gpio.inc b/board/reef/gpio.inc
index 265ff8c25b..187739a77a 100644
--- a/board/reef/gpio.inc
+++ b/board/reef/gpio.inc
@@ -9,7 +9,7 @@
* Note: Those with interrupt handlers must be declared first. */
GPIO_INT(PD_MCU_INT, PIN(3, 3), GPIO_INT_LOW, pd_mcu_interrupt) /* CHARGER_EC_INT_ODL from BD99955 */
-GPIO_INT(USB_C0_PD_INT, PIN(3, 7), GPIO_INT_RISING | GPIO_SEL_1P8V, tcpc_alert_event) /* from Analogix TCPC */
+GPIO_INT(USB_C0_PD_INT, PIN(3, 7), GPIO_INT_RISING, tcpc_alert_event) /* from Analogix TCPC */
GPIO_INT(USB_C1_PD_INT_ODL, PIN(D, 2), GPIO_INT_FALLING, tcpc_alert_event) /* from Parade TCPC */
GPIO_INT(PCH_SLP_S4_L, PIN(8, 6), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S4_L */