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authorJenny TC <jenny.tc@intel.com>2017-05-24 18:12:32 +0530
committerchrome-bot <chrome-bot@chromium.org>2017-07-24 03:03:47 -0700
commit43081fded2ee9976dc16b1f5bd72bcade33c33d7 (patch)
tree9363e4d56e73d0745596cba97582c6797cf8985f /board/reef
parentd7f7f6931766472fab94726e82dc9b172f9c10a5 (diff)
downloadchrome-ec-43081fded2ee9976dc16b1f5bd72bcade33c33d7.tar.gz
S0ix: use both SLP_S0 interrupt and host command for s0ix
EC currently uses a host command from kernel to enter s0ix. This patch waits for the SLP_S0 interrupt to come after receiving the host command before entering S0ix. On the exit path, the SLP_S0 interrupt directly triggers the exit rather than waiting for the host command. BRANCH=none BUG=b:37443151 TEST=check in EC logs for SLP_S0 entry and powerindebug output, check suspend_stress_test on reef and soraka works fine, make -j8 buildall runs fine Change-Id: Ie5507b7a1e723532f07bc0671c2abd364f6224a2 Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Signed-off-by: Archana Patni <archana.patni@intel.com> Signed-off-by: Jenny TC <jenny.tc@intel.com> Reviewed-on: https://chromium-review.googlesource.com/513705 Commit-Ready: Jenny Tc <jenny.tc@intel.com> Tested-by: Jenny Tc <jenny.tc@intel.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Diffstat (limited to 'board/reef')
-rw-r--r--board/reef/board.c3
-rw-r--r--board/reef/board.h5
-rw-r--r--board/reef/gpio.inc5
3 files changed, 12 insertions, 1 deletions
diff --git a/board/reef/board.c b/board/reef/board.c
index 80b836099c..786a8e56b3 100644
--- a/board/reef/board.c
+++ b/board/reef/board.c
@@ -125,6 +125,9 @@ void tablet_mode_interrupt(enum gpio_signal signal)
/* power signal list. Must match order of enum power_signal. */
const struct power_signal_info power_signal_list[] = {
+#ifdef CONFIG_POWER_S0IX
+ {GPIO_PCH_SLP_S0_L, 1, "SLP_S0_DEASSERTED"},
+#endif
{GPIO_RSMRST_L_PGOOD, 1, "RSMRST_L"},
{GPIO_PCH_SLP_S3_L, 1, "SLP_S3_DEASSERTED"},
{GPIO_PCH_SLP_S4_L, 1, "SLP_S4_DEASSERTED"},
diff --git a/board/reef/board.h b/board/reef/board.h
index c9d5b15f86..b9b613d654 100644
--- a/board/reef/board.h
+++ b/board/reef/board.h
@@ -240,7 +240,10 @@ enum pwm_channel {
};
enum power_signal {
- X86_RSMRST_N = 0,
+#ifdef CONFIG_POWER_S0IX
+ X86_SLP_S0_N,
+#endif
+ X86_RSMRST_N,
X86_SLP_S3_N,
X86_SLP_S4_N,
X86_SUSPWRDNACK,
diff --git a/board/reef/gpio.inc b/board/reef/gpio.inc
index fb45f2336b..8ea62c0590 100644
--- a/board/reef/gpio.inc
+++ b/board/reef/gpio.inc
@@ -19,6 +19,9 @@ GPIO_INT(USB_C1_PD_INT_ODL, PIN(B, 1), GPIO_INT_FALLING | GPIO_PULL_UP, tcpc_ale
GPIO_INT(USB_C0_CABLE_DET, PIN(C, 5), GPIO_INT_RISING, anx74xx_cable_det_interrupt) /* CABLE_DET from ANX3429 */
+#ifdef CONFIG_POWER_S0IX
+GPIO_INT(PCH_SLP_S0_L, PIN(7, 5), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S0_L */
+#endif
GPIO_INT(PCH_SLP_S4_L, PIN(8, 6), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S4_L */
GPIO_INT(PCH_SLP_S3_L, PIN(7, 3), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S3_L */
GPIO_INT(SUSPWRNACK, PIN(7, 2), GPIO_INT_BOTH, power_signal_interrupt)
@@ -69,7 +72,9 @@ GPIO(EC_I2C_POWER_SCL, PIN(D, 1), GPIO_INPUT)
GPIO(PCH_SMI_L, PIN(A, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V) /* EC_SMI_ODL */
GPIO(PCH_SCI_L, PIN(A, 7), GPIO_ODR_HIGH | GPIO_SEL_1P8V) /* EC_SCI_ODL */
+#ifndef CONFIG_POWER_S0IX
GPIO(PCH_SLP_S0_L, PIN(7, 5), GPIO_INPUT) /* SLP_S0_L */
+#endif
/*
* BRD_ID1 is a an ADC pin which will be used to measure multiple values.