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| author | Vijay Hiremath <vijay.p.hiremath@intel.com> | 2018-03-22 04:55:51 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-03-24 07:32:29 -0700 |
| commit | 3bd4e0de5edc6f62eda8739d31816b5b29d1979b (patch) | |
| tree | d6cc7049652e5fc41b765e0708e8722e4ca7bd24 /board/reef_it8320/gpio.inc | |
| parent | f59290878e5fcd99add71aec74baea7d1e3f0297 (diff) | |
| download | chrome-ec-3bd4e0de5edc6f62eda8739d31816b5b29d1979b.tar.gz | |
Code cleanup: Rename GPIO PCH_RCIN_L to SYS_RESET_L
Renamed GPIO PCH_RCIN_L to SYS_RESET_L so that all the Intel
chipset variants have same GPIO name for doing SOC internal reset.
BUG=b:72426192
BRANCH=none
TEST=make buildall -j
Change-Id: I931ce136743fa928dd7cf6f005c912db3b2da893
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/974241
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Diffstat (limited to 'board/reef_it8320/gpio.inc')
| -rw-r--r-- | board/reef_it8320/gpio.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/reef_it8320/gpio.inc b/board/reef_it8320/gpio.inc index eee4835880..3d26bde426 100644 --- a/board/reef_it8320/gpio.inc +++ b/board/reef_it8320/gpio.inc @@ -40,7 +40,7 @@ GPIO(WIRELESS_GPIO_WLAN_POWER, PIN(B, 2), GPIO_ODR_HIGH) /* EN_PP3300_WLAN_ODL GPIO(EC_I2C_A_SCL, PIN(B, 3), GPIO_INPUT | GPIO_SEL_1P8V) /* EC_I2C_GYRO_SCL */ GPIO(EC_I2C_A_SDA, PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V) /* EC_I2C_GYRO_SDA */ GPIO(ENABLE_BACKLIGHT, PIN(B, 5), GPIO_ODR_HIGH | GPIO_SEL_1P8V) /* EC_BL_EN_OD */ -GPIO(PCH_RCIN_L, PIN(B, 6), GPIO_ODR_HIGH) /* SYS_RST_ODL */ +GPIO(SYS_RESET_L, PIN(B, 6), GPIO_ODR_HIGH) /* SYS_RST_ODL */ #ifndef CONFIG_POWER_S0IX GPIO(PCH_SLP_S0_L, PIN(B, 7), GPIO_INPUT) /* SLP_S0_L */ #endif |