diff options
| author | Jenny TC <jenny.tc@intel.com> | 2017-05-24 18:12:32 +0530 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-07-24 03:03:47 -0700 |
| commit | 43081fded2ee9976dc16b1f5bd72bcade33c33d7 (patch) | |
| tree | 9363e4d56e73d0745596cba97582c6797cf8985f /board/reef_it8320 | |
| parent | d7f7f6931766472fab94726e82dc9b172f9c10a5 (diff) | |
| download | chrome-ec-43081fded2ee9976dc16b1f5bd72bcade33c33d7.tar.gz | |
S0ix: use both SLP_S0 interrupt and host command for s0ix
EC currently uses a host command from kernel to enter s0ix.
This patch waits for the SLP_S0 interrupt to come after receiving
the host command before entering S0ix.
On the exit path, the SLP_S0 interrupt directly triggers the
exit rather than waiting for the host command.
BRANCH=none
BUG=b:37443151
TEST=check in EC logs for SLP_S0 entry and powerindebug output,
check suspend_stress_test on reef and soraka works fine,
make -j8 buildall runs fine
Change-Id: Ie5507b7a1e723532f07bc0671c2abd364f6224a2
Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Signed-off-by: Archana Patni <archana.patni@intel.com>
Signed-off-by: Jenny TC <jenny.tc@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/513705
Commit-Ready: Jenny Tc <jenny.tc@intel.com>
Tested-by: Jenny Tc <jenny.tc@intel.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Diffstat (limited to 'board/reef_it8320')
| -rw-r--r-- | board/reef_it8320/board.c | 3 | ||||
| -rw-r--r-- | board/reef_it8320/board.h | 5 | ||||
| -rw-r--r-- | board/reef_it8320/gpio.inc | 5 |
3 files changed, 12 insertions, 1 deletions
diff --git a/board/reef_it8320/board.c b/board/reef_it8320/board.c index 06259c0c6a..e2abb87957 100644 --- a/board/reef_it8320/board.c +++ b/board/reef_it8320/board.c @@ -60,6 +60,9 @@ /* power signal list. Must match order of enum power_signal. */ const struct power_signal_info power_signal_list[] = { +#ifdef CONFIG_POWER_S0IX + {GPIO_PCH_SLP_S0_L, 1, "SLP_S0_DEASSERTED"}, +#endif {GPIO_RSMRST_L_PGOOD, 1, "RSMRST_L"}, {GPIO_PCH_SLP_S3_L, 1, "SLP_S3_DEASSERTED"}, {GPIO_PCH_SLP_S4_L, 1, "SLP_S4_DEASSERTED"}, diff --git a/board/reef_it8320/board.h b/board/reef_it8320/board.h index 62324ff519..67066a0675 100644 --- a/board/reef_it8320/board.h +++ b/board/reef_it8320/board.h @@ -172,7 +172,10 @@ enum adc_channel { }; enum power_signal { - X86_RSMRST_N = 0, +#ifdef CONFIG_POWER_S0IX + X86_SLP_S0_N, +#endif + X86_RSMRST_N, X86_SLP_S3_N, X86_SLP_S4_N, X86_SUSPWRDNACK, diff --git a/board/reef_it8320/gpio.inc b/board/reef_it8320/gpio.inc index bad4ece3e0..5a09785e0d 100644 --- a/board/reef_it8320/gpio.inc +++ b/board/reef_it8320/gpio.inc @@ -15,6 +15,9 @@ GPIO_INT(UART1_RX, PIN(B, 0), GPIO_INT_FALLING, uart_deepsleep_interrupt) /* UA #endif GPIO_INT(EC_VOLUP_BTN_ODL, PIN(D, 5), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) /* EC_VOLUP_BTN_ODL */ GPIO_INT(EC_VOLDN_BTN_ODL, PIN(D, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) /* EC_VOLDN_BTN_ODL */ +#ifdef CONFIG_POWER_S0IX +GPIO_INT(PCH_SLP_S0_L, PIN(B, 7), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S0_L */ +#endif GPIO_INT(SUSPWRNACK, PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt) /* SUSPWRNACK */ GPIO_INT(LID_OPEN, PIN(E, 2), GPIO_INT_BOTH, lid_interrupt) /* LID_OPEN */ GPIO_INT(PCH_PLTRST_L, PIN(E, 3), GPIO_INT_BOTH | GPIO_PULL_UP, lpcrst_interrupt) /* PLT_RST_L */ @@ -36,7 +39,9 @@ GPIO(EC_I2C_A_SCL, PIN(B, 3), GPIO_INPUT | GPIO_SEL_1P8V) /* EC_I2C_GYRO_SCL * GPIO(EC_I2C_A_SDA, PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V) /* EC_I2C_GYRO_SDA */ GPIO(ENABLE_BACKLIGHT, PIN(B, 5), GPIO_ODR_HIGH | GPIO_SEL_1P8V) /* EC_BL_EN_OD */ GPIO(PCH_RCIN_L, PIN(B, 6), GPIO_ODR_HIGH) /* SYS_RST_ODL */ +#ifndef CONFIG_POWER_S0IX GPIO(PCH_SLP_S0_L, PIN(B, 7), GPIO_INPUT) /* SLP_S0_L */ +#endif GPIO(EC_BATT_PRES_L, PIN(C, 0), GPIO_INPUT) /* EC_BATT_PRES_L */ GPIO(EC_I2C_B_SCL, PIN(C, 1), GPIO_INPUT | GPIO_SEL_1P8V) /* EC_I2C_SENSOR_U_SCL */ GPIO(EC_I2C_B_SDA, PIN(C, 2), GPIO_INPUT | GPIO_SEL_1P8V) /* EC_I2C_SENSOR_U_SDA */ |