diff options
| author | Gwendal Grignou <gwendal@chromium.org> | 2015-07-25 02:49:00 -0700 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-07-30 19:58:09 +0000 |
| commit | ff550b0e1abfc97a8531eed5515c75e0f37deba3 (patch) | |
| tree | 9a9148a436f719437996d4703e2198942b9b5b3d /board/ryu/gpio.inc | |
| parent | a3a5c90b54670ddc865defc16757f1fef78ca322 (diff) | |
| download | chrome-ec-ff550b0e1abfc97a8531eed5515c75e0f37deba3.tar.gz | |
stm32: Enable 3rd SPI interface
Remove assumption of only one SPI master going to the SPI flash.
SPI3 can be used as second SPI master.
Define a new module type, SPI_FLASH, that can be turned
on/off when flash is not in used without impacting other
SPI masters.
BRANCH=smaug
BUG=chrome-os-partner:42304
TEST=Test on Ryu board.
Change-Id: Ie72471cea6f0a357ffee055a610d032580a794e7
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/288514
Diffstat (limited to 'board/ryu/gpio.inc')
| -rw-r--r-- | board/ryu/gpio.inc | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/board/ryu/gpio.inc b/board/ryu/gpio.inc index 009bfd98a2..45e839c113 100644 --- a/board/ryu/gpio.inc +++ b/board/ryu/gpio.inc @@ -130,11 +130,11 @@ UNIMPLEMENTED(AP_RESET_L) #define GPIO_ODR_UP GPIO_OPEN_DRAIN | GPIO_PULL_UP -ALTERNATE(PIN_MASK(B, 0xC400), 5, MODULE_SPI_MASTER, 0) /* SPI2: PB10/14/15 */ -ALTERNATE(PIN_MASK(B, 0x0008), 5, MODULE_USB_PD, 0) /* SPI1: SCK(PB3) */ -ALTERNATE(PIN_MASK(B, 0x0002), 2, MODULE_USB_PD, 0) /* TIM3_CH4: PB1 */ -ALTERNATE(PIN_MASK(B, 0x00C0), 7, MODULE_USART, 0) /* USART1: PB6/PB7 */ -ALTERNATE(PIN_MASK(D, 0x0060), 7, MODULE_UART, GPIO_PULL_UP) /* USART2: PD4/PD5 */ -ALTERNATE(PIN_MASK(C, 0x0C00), 7, MODULE_USART, GPIO_ODR_UP) /* USART3: PC10/PC11 */ -ALTERNATE(PIN_MASK(A, 0xC600), 4, MODULE_I2C, 0) /* I2C SLAVE:PA9/10 MASTER:PA14/15 */ -ALTERNATE(PIN_MASK(A, 0x1800),14, MODULE_USB, 0) /* USB: PA11/12 */ +ALTERNATE(PIN_MASK(B, 0xC400), 5, MODULE_SPI_FLASH, 0) /* SPI2: PB10/14/15 */ +ALTERNATE(PIN_MASK(B, 0x0008), 5, MODULE_USB_PD, 0) /* SPI1: SCK(PB3) */ +ALTERNATE(PIN_MASK(B, 0x0002), 2, MODULE_USB_PD, 0) /* TIM3_CH4: PB1 */ +ALTERNATE(PIN_MASK(B, 0x00C0), 7, MODULE_USART, 0) /* USART1: PB6/PB7 */ +ALTERNATE(PIN_MASK(D, 0x0060), 7, MODULE_UART, GPIO_PULL_UP) /* USART2: PD4/PD5 */ +ALTERNATE(PIN_MASK(C, 0x0C00), 7, MODULE_USART, GPIO_ODR_UP) /* USART3: PC10/PC11 */ +ALTERNATE(PIN_MASK(A, 0xC600), 4, MODULE_I2C, 0) /* I2C SLAVE:PA9/10 MASTER:PA14/15 */ +ALTERNATE(PIN_MASK(A, 0x1800),14, MODULE_USB, 0) /* USB: PA11/12 */ |